JPS61168446U - - Google Patents
Info
- Publication number
- JPS61168446U JPS61168446U JP4759685U JP4759685U JPS61168446U JP S61168446 U JPS61168446 U JP S61168446U JP 4759685 U JP4759685 U JP 4759685U JP 4759685 U JP4759685 U JP 4759685U JP S61168446 U JPS61168446 U JP S61168446U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bus line
- buffer circuit
- power consumption
- low power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4759685U JPH04440Y2 ( ) | 1985-04-03 | 1985-04-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4759685U JPH04440Y2 ( ) | 1985-04-03 | 1985-04-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61168446U true JPS61168446U ( ) | 1986-10-18 |
| JPH04440Y2 JPH04440Y2 ( ) | 1992-01-08 |
Family
ID=30563071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4759685U Expired JPH04440Y2 ( ) | 1985-04-03 | 1985-04-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04440Y2 ( ) |
-
1985
- 1985-04-03 JP JP4759685U patent/JPH04440Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04440Y2 ( ) | 1992-01-08 |