JPS61168430U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a coincidence detection circuit according to an embodiment of the invention, FIG. 2 is a timing chart showing the operation of each part of the coincidence detection circuit shown in FIG. 1, and FIG. 3 is a conventional coincidence detection circuit. FIG. 3 is a diagram showing an example of the configuration of a detection circuit. In the figure, 1 is a data input terminal, 7 is a latch circuit, 8 is a word unit n consecutive match data output terminal, 9 is a shift register SR, 10 is an exclusive OR circuit, and 11 is a D-type flip-flop with reset. , 13 is a shift register SR, and 14 is an NAND circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A digital data shift circuit that serially shifts input digital data by the sum of a predetermined word length and 1 bit and outputs the result; A comparison circuit compares and outputs the bits at the same position of each word, and based on the output signal from this comparison circuit, it is determined that all the bits at the same position of each word match between the two adjacent words. A first determination circuit that outputs a predetermined signal at some time, and a preset number of times that a word in which all bits at the same position match based on the signal output from the first determination circuit and serially shifted. and a second determination circuit that outputs a predetermined signal when it is determined that the signals have appeared consecutively, and when the signal is output from the digital data shift circuit and the determination is made by the second determination circuit. A coincidence detection circuit configured to latch digital data based on an output signal from the second determination circuit.