JPS61168195A - Static type semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To obtain a static type storage circuit which has a high response speed without increasing the chip area by varying the P-N junction capacity of some of memory cells arranged in a matrix of plural rows and columns. CONSTITUTION:The matrix array consists of storage cells Ekj, digit line load elements LkN, decoding output word lines W1K, digit line couples Dk1 and Dk2, digit signal transfer gates Qk1 and Qk2, digit selection lines Y1k, data lines D10 and D20, and reference potential V00(V701) and V01(V702). Each storage cell E have load elements L701 and L702, drivers Q701 and Q702, and transfer gates Q703 and Q704 connected as specified and a potential V1101 lower than a reference potential V702 is applied during reading operation. At this time, transfer gates Q703 and Q704 formed in the N well of a P substrate are applied with the V1101 at an electrode 807 to reduce the junction capacity and increase the response speed. Therefore, the Q703 and Q704 need not be increased in size for speed improvement and there is no increase in chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a static semiconductor memory circuit.

(Description of Prior Art) In recent years, static semiconductor memory circuits have been widely used in computers, control equipment, and the like.

In the following description, unless a static semiconductor memory circuit is specified, the substrate is an N-type semiconductor, and the memory cell portion is an N-channel semiconductor.
An example of a circuit will be explained in which the circuit is composed of four metal-oxide semiconductor (NMO8) transistors and two resistive elements, and the peripheral circuit section is composed of complementary metal-oxide semiconductor (0MO8) transistors.

FIG. 1 is a block diagram of a static semiconductor memory circuit having a decoding function.
1. Address decoder circuit section] 02°Memory cell array section 103. Sense amplification circuit section 104° control circuit section 105
．． Write/read control circuit section 106. Output buffer circuit section 1
It is made up of more than 07.

FIG. 2 shows a read timing diagram and a write timing diagram of the static semiconductor memory circuit shown in FIG. 1. Next, read operation and write operation will be explained with reference to FIGS. 1, 2, and 3.

In a read operation, an address signal AI)D is applied to the address buffer circuit section 101, and the decoded signal is transferred to a specified address of the memory cell array section 103 via the address decoder circuit section 102, and an arbitrary address is be accessed. Information in the memory cell array section 103 is transferred to the sense amplification circuit section 104 and outputted as an output signal Do via the output circuit section 107. At this time, the control signal C8 needs to be activated, and the control circuit section 105 generates the control signal. Note that the write signal W
E needs to be in a read instruction state, and at this time, the convolution data signal DIN ld may be arbitrary.

The write operation is similar to the read operation, but the write control signal WE is in a write instruction state, and the read/write control circuit unit 106
is applied to At this time, the write data signal DIN needs to be at high level or low level.

FIG. 4 shows a specific circuit example of the memory cell array section 103 of a conventional static type memory circuit. Internal memory circuit CK
J (K=1-4.J=1-4), digit line load element LKN (K=1-4, l'1J=l, 2).

Decoder output word line W/K (K=l~4), digit line pair f)Kl(K=1~4), 1)K2(K=1~4)
), Gagit signal transfer gate QKI (K=1~.i)
, QK2 (K=1 to 4), digit selection line Y IK (
K=1-4), data lines DlO, D20. Reference potential line v
It is composed of many things like oo and vol.

As an example of the circuit operation of this circuit, a read operation for reading out stored information in the internal storage circuit C11 will be described. Note that FIGS. 5 and 6 show a read timing diagram and a W-include timing diagram, respectively.

4 and 5, in order to read out the information stored in the internal storage circuit C1l, by setting the word line W11 to a high level, the information stored in the internal storage circuits CIl-C14 is read out from the digit lines DIl-D14. D12 to D24, select Yll of digit selection signals Y11 to Y14, set digit line signal transfer) Qll and Q12 to selected state,
The digital line pair DI1, DI2F) is transferred to the data lines DIO, D20, and the information ``1# or 0'' is extracted.

The operation of storing information into the internal memory circuit C1l is shown in FIGS. 4 and 6.
As is clear from the figure, the word line Wll is set to high level,
Whether the write information is 'l#' or 'O#', the active line pair 1
)11. This is executed by setting the 10,000 FAi level of DI2 and the other to a low level.

A specific example of CKJ (K=l-4.J=1-4) in FIG. 4 is shown in the broken line section CK in FIG. Figure 7 shows load elements L701, L
702. Transfer transistor Q703, Q
704, driver transistor Q701,
-Q702, one end of the load element is connected to the first reference potential line V701, and the source terminals of the driver transistors Q701 and Q702 and the source-drain junctions of the transistors Q701 to Q704 are connected to the second reference potential line V702. It is connected to the. Also, transfer transistor Q703. The gate terminal of Q704 is connected to word line W701, and the source terminal is connected to digit line D7.
01 and D702, respectively. The reference potential lines Voo and Vo1 in FIG. 4 are the reference potential lines Voo and Vo1 in FIG.
701. It is compatible with V7024C.

FIG. 8 shows a schematic cross-sectional structure of transfer transistor Q703 shown in FIG. 7, and FIG. 9 shows an equivalent circuit diagram of FIG. 8.

As shown in FIG. 8, the transfer transistor=6-Q703 is connected to an N-type semiconductor substrate 801. P-type semiconductor layer 80
2. N-type semiconductor layers 803, 804, oxide film 80
It consists of 5 parts. Here, metal layers and other insulating layers are omitted.

Terminals 808, 809, 810 shown in FIG. 8 correspond to digit lines D701. The word line W701 corresponds to the intersection terminal N710 of the transfer transistor Q703 and the load element L701, respectively, and the terminals 807 and 811 correspond to the reference potential line V702. Each corresponds to V701.

(Problems to be Solved by the Invention) In reading from the internal storage circuit C11 shown in FIGS. 4 and 7, transfer transistor Q703. Q704
Since the digit line junction capacitance of all the cells connected to the digit lines Dll and D12 must be discharged, the digit response becomes slow. In the conventional static semiconductor memory circuit described above, transfer transistors Q703 . Although it would be good to make Q704 thicker and strengthen its current capacity, it had the disadvantage of increasing the chip area.

(Object of the Invention) The present invention was proposed in order to eliminate the drawbacks of the conventional circuit, and to provide a static semiconductor memory circuit with a fast response speed without increasing the chip area. purpose.

(Means for Solving the Problems) The present invention provides a static semiconductor memory circuit including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, in which at least a part of the P-type semiconductor and the N-type semiconductor The semiconductor device is characterized by comprising a junction capacitance changing means for changing the junction capacitance of the type semiconductor.

The junction capacitance changing means of the present invention includes a first and a second transistor, each having a drain connected to a first reference potential via a first or a second load element and a source connected to a second reference potential. a first transfer transistor whose drain is connected to the drain of the first driver transistor and the gate of the second driver transistor and whose source is connected to the first digit line and whose drain is connected to the second driver transistor; a second transfer transistor connected to the drain of the transistor and the gate of the first driver transistor and whose source is connected to a second digit line; the word line is connected to the gates of each of the first and second transfer transistors; A third reference potential may be connected to the source-drain junctions of the first and second transfer transistors of the memory cell connected to the third reference potential.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 10 shows a 4 word x 4 bit cell array section.
Internal memory circuit BKJ (K=1-4.J=1-4), digit line load element LKN (K=1-4°N=1-4),
Decode output word line WIK (K=1-4), digit line pair DK1 (K=t-4).

DK2 (K=1~4), digital signal transfer gate QK
l (K=l~4), QK2 (K=1~4), Digi,
Data selection line YIK (K=1-4), data line D10°D2
0. It is composed of reference potential lines VOO and VOI, and is the same as the conventional example shown in FIG. 4 except that an internal storage circuit E11 is used in place of the internal storage circuit C1l. 1st
Internal storage circuit EKJ (K=1~4.J==1~4 in Figure 0)
) is shown in broken line section E in FIG.

FIG. 11 shows load elements L701, L702. It is composed of transfer transistors Q701 and Q702, one end of the load element is connected to the first reference potential 1V701, the source terminals of the driver transistors Q701 and Q702 are connected to the second reference potential line 702, and the transistors Q701. Q702. Q703. The P-type semiconductor layer of the source and drain junction of Q704 is connected to the third reference potential line VIIOI. Reference potential line V in Figure 10
OO and VOI can also be shown in the cross-sectional structure of the reference potential Q703 in FIG. 11 in the same way as in FIG.

As is clear from the above description, in FIGS. 10 and 11, transfer transistor Q703. The digit capacity of Q704 is variable by controlling the third reference potential line 1101. By applying a more negative potential to the third reference potential line VIIOI than to the second reference potential line 702, a large reverse bias can be applied to the digit line junction and the junction capacitance of the digit line can be reduced. , it becomes possible to increase the digit line response speed. Therefore, a high-speed static semiconductor memory circuit can be realized without increasing the chip area.

Although the third reference potential line VIIOI in FIG. 11 can be supplied from an external terminal, FIG. 12 shows a circuit embodiment in which the lowest potential is generated within the same chip.

Figure 12 shows an oscillation circuit consisting of inverters IOI to IO3, a capacitor C1201, and a rectifier diode Q1201.
, Q1202 is an example of a circuit that generates the lowest potential.

Note that in this embodiment, driver transistors Q701. The junction capacitance of Q702 is also variable.

It is clear that the present invention can be modified in various ways other than the static semiconductor memory circuit shown in the embodiments within the scope of the claims.

For example, digit line signal transfer game) QKI, QK
The junction capacitance of the transfer gates QKI and QK2 can also be made variable by connecting the third reference potential line VIIOI to the source/drain junctions of the transfer gates QKI and QK2. Further, the junction capacitance of the transistors constituting the address decoder circuit section, the sense amplification circuit section, etc. can also be made variable.

(Effects of the Invention) As explained above, the static semiconductor memory circuit of the present invention is provided with a junction capacitance changing means for changing the junction capacitance of a P-type semiconductor and an N-type semiconductor, thereby achieving high speed and stability with a small chip area. This has the effect of allowing you to obtain the desired action.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a general static semiconductor memory circuit, and FIGS. 2 and 3 show the state shown in FIG.
FIG. 4 is a circuit diagram of a memory cell array section of a conventional static semiconductor memory circuit, and FIGS. 7 is a timing diagram of a read operation and a timing diagram of a write operation of the memory cell array section shown in FIG.
9 and 9 are a schematic cross-sectional view and an equivalent circuit diagram of the transfer transistor Q703 shown in FIG. 7, FIG. 10 is a circuit diagram of a memory cell array portion of a static semiconductor memory circuit according to an embodiment of the present invention, and FIG. is the circuit diagram of the internal storage circuit EKJ shown in Fig. 10, and Fig. 12 is the circuit diagram of the internal storage circuit EKJ shown in Fig. 11 VC.
FIG. 13 is a circuit diagram of an example of a circuit for generating the lowest potential to be applied to the third reference potential line VIIOI shown in FIG. 101...Address buffer circuit section, 102.
...Address decoder circuit section, 103...
-Memory cell array section, 104...Sense amplification circuit section, 105...Control circuit section, 106...
...Write/read control circuit section, 107...Output buffer circuit section, 801...N-type semiconductor substrate,
802...P-type semiconductor substrate, 803.804.
...N-type semiconductor layer, 805... Oxide film,
CIl~C44, Ell~E44...Internal memory port/path, DIl~D41', D12~D42, D70
1, D702... digit line, L)10.
D20...Data line, Lll to L41. L12
~L42. L701, L702...Load element, Q11 to Q41. Q12 to Q42... Digit signal transfer gate, Q701, Q702...
・Driver transistor, Q703, Q704...
...Transfer transistor, V2O3, V2O3
, VIIOI...Reference potential line, Wll to W14
．． W2O3...Word line. W[ Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) Junction capacitance change that changes the junction capacitance of at least some P-type semiconductors and N-type semiconductors in a static semiconductor memory circuit that includes multiple memory cells arranged in a matrix of multiple rows and multiple columns. A static semiconductor memory circuit characterized by comprising means. (2) In the junction capacitance changing means, each drain is connected to the first
or a first load element connected to the first reference potential via a second load element and each source of which is connected to the second reference potential;
and a first transfer transistor whose drain is connected to the drain of the first driver transistor and the gate of the second driver transistor and whose source is connected to the first digit line and whose drain is connected to the first digit line. a second transfer transistor connected to the drain of the second driver transistor and the gate of the first driver transistor and whose source is connected to the second digit line, and the word line is connected to the first and second transfer transistors. the sources of the first and second transfer transistors of the memory cell connected to their respective gates;
The static semiconductor memory circuit according to claim 1, wherein the third reference potential is connected to the drain junction.