JPS6116704Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that allows random access while using a charge transfer element.

Generally, a charge transfer element has electrodes E ₁ , E _{2 .} . . as shown in FIG. 1, and charges are transferred by applying a voltage to these electrodes E ₁ and the like. Now, let x be the charge transfer direction, and define the electrode length L in the same direction and the electrode width W in the direction orthogonal to this. In the normal case, L<W, and the shorter the electrode length L, the more the charge is Transfer efficiency is good.

However, even if the charge transfer efficiency is slightly reduced, by using a charge transfer element having an electrode long in the charge transfer direction, a new device can be obtained that takes advantage of its characteristics.

The present invention uses a charge transfer element having a long electrode extending in the charge transfer direction as a bit line, and combines this with a memory cell composed of an ordinary charge transfer element to transfer charge, which previously could only function like a shift register. A semiconductor memory device using a transfer element can be provided with a random access function, which will be described in detail below.

Normally, the mode of charge transfer of a charge transfer element is considered to be a drift current component and a diffusion current component, but as the electrode length L becomes large, the drift current component cannot be expected, and the diffusion current component becomes dominant.

Now, as seen in FIG. 2a, a silicon dioxide insulating layer IS and an electrode E ₁ are formed on a silicon semiconductor substrate SB.
When considering ^a _charge transfer system in which E ₂ .
Note that D is the diffusion constant of the carrier, and if it is an electron, it is expressed as De.

Fig. 2b shows the state in which the electric charge existing under the electrode _E1 is transferred to the underside of the electrode _E2 when the electrodes E1 and _E2 are at the same potential, and Fig. 2c shows the state where the electric charge existing under the electrode _E1 is transferred to the underside of the electrode _E2 . As _{the potential} at
It represents the state of being pushed downwards.

Now, in the state shown in Figure 2b, from electrode _E1
To transfer 50% of charge to E ₂ , τ _F /100 ~ τ _F
A time of /10 is sufficient, and in the state shown in FIG. 2c, a time of τ _F is sufficient to achieve a sufficient extrusion effect and transfer 99%.

Therefore, let us consider a charge transfer system as shown in FIG.

In the figure, E ₁₁ , E ₁₂ , E ₁₃ , E ₁₄ , and E ₁₅ are electrodes, and the electrode lengths L of the electrodes E ₁₁ , E ₁₂ , E ₁₄ , and E ₁₅ are small like normal charge transfer elements. , the transfer efficiency is
The electrode length L of the electrode E 13 is about 99.9 [%], and the electrode length L of the electrode E ₁₃ is large, and L≫W, for example, L = 100 to 1000.
Suppose that it is [μm].

Now, L=100 [μm], De≒3.5×10 ^-3 [m ² /
seconds], then τ _F = (0.1×10 ⁻³ ) ² /2.46×3.5×
10 ⁻³ 〓1.16 [μs].

In addition, L = 50 [μm], and the fall of the pulse applied to the electrode (which affects charge extrusion) is 70
When [n _s ], the transfer efficiency is said to be 99.7 [%]. When L=50 [μm], τ _F 〓290
Since [n _s ], τ/τ _F =70/290〓0.24 where L<W. Note that τ is the fall time of the transfer pulse and determines the charge pushing effect.

As can be understood from the above description, for example, the electric charge under the electrode E ₁₁ is transferred to the bottom of the electrode E ₁₅ at a considerable speed through the regions corresponding to the electrodes E ₁₂ , E ₁₃ , and E ₁₄ . Can be done.

By the way, if there is a charge transfer system as shown in Fig. 3, it is possible to use it to obtain a random access memory device.This semiconductor memory device has a large capacity although it is a little slow, and is easy to manufacture. Become something.

FIG. 4 is an explanatory diagram of one embodiment of the present invention, in which the same parts as those explained in connection with FIG. 3 are indicated by the same symbols.

In the figure, WL ₁ , WL ₂ ...WL _1o , WL _2o are word lines, D ₁ , D ₂ are impurity diffusion regions, CT is peripheral circuit,
_φ1 ... _φ5 are clock signals, and Re is a reset terminal, respectively.

In the illustrated example, electrodes E ₁₁ and E ₁₂ constitute one memory cell. That is, information signals (charges) are accumulated in the region corresponding to the electrode _E11 using the same principle as a normal charge transfer element, and the region corresponding to the electrode _E11 is stored depending on whether or not the electrode _E12 is selected based on the word line _WL2 . It is used to select or non-select information signals accumulated in a region. electrode
_E13 corresponds to a bit line and may be made of polycrystalline silicon, for example. Note that the word line WL ₁ and the like are made of metal such as aluminum. Electrode E ₁₃
Also, information signals can be transferred using exactly the same principle as charge transfer devices. The peripheral circuit CT includes necessary circuits such as a sense circuit, a read/write control circuit, a refresh control circuit, an output circuit, etc., and these may be composed of MIS field effect transistors.

In this device, for example, when reading out an information signal,
A clock signal φ ₅ is applied to the electrode E ₁₃ which is a bit line, and the information signal accumulated in the word line WL ₂ and thus the area corresponding to the electrode E ₁₁ selected by the electrode E ₁₂ is transferred to the bit line WL 2 by the electrode E ₁₃ . For example, the signals are transferred and read out through the respective regions corresponding to the electrodes E ₁₄ and E ₁₅ to which the clock signals φ ₁ and φ ₂ are applied, for example. Since the electrode _E13 , which is a bit line, has a long electrode length L, the clock signal _φ5 must have a waveform as shown in the figure, and its fall must be gradual to obtain a sufficient pushing effect. Furthermore, the electrode
If E ₁₃ is taken too long, the transfer efficiency will decrease, so
For example, about 100 to 500 [μm] is considered suitable.

As can be seen from the above explanation, according to the present invention, although it is a memory device that uses a charge transfer element, random access is possible, and furthermore, an impurity diffusion region is not required in the memory cell, so it is highly efficient. It can be integrated, and the refresh time can be increased. Therefore, it is possible to easily manufacture a large-capacity storage device, albeit at a slightly slower speed.

Furthermore, the charge accumulated in the charge transfer element consisting of a long electrode is transferred to the selected memory cell by applying a clock signal for charge transfer to the long electrode, resulting in high sensitivity. It becomes possible to detect information.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams for explaining the operation of the charge transfer device, FIG. 3 is an explanatory diagram for explaining the principle of the present invention, and FIG. 4 is an explanatory diagram for explaining an embodiment of the present invention. It is. E ₁₁ ~ E ₁₅ ... Electrode, WL ₁ , WL ₂ ... WL _1o ,
WL _2o ... Word line, D ₁ , D ₂ ... Impurity diffusion region,
CT...peripheral circuit, _φ1 to _φ5 ...clock signals, respectively.

Claims (1)

[Scope of utility model registration request] a plurality of storage cells configured as a set of two charge transfer elements with electrodes connected to separate word lines;
a long electrode formed along one electrode of the plurality of memory cells; a pair of electrodes disposed at the ends of the long electrode; and a diffusion disposed adjacent to one of the pair of electrodes. layer and a peripheral circuit connected to the diffusion layer are formed on a semiconductor substrate, and charges accumulated in the semiconductor substrate under the electrode constituting the selected memory cell are transferred to the semiconductor substrate under the long electrode. A charge transfer clock signal having a waveform with a slow fall relative to rise is applied to the long electrode, and the charge transferred into the semiconductor substrate under the long electrode is pushed out to the pair of electrodes. A semiconductor memory device characterized in that the charge is transferred into the underlying semiconductor substrate and further transferred to the peripheral circuit via the diffusion layer.