JPS61165054U

JPS61165054U -

Info

Publication number: JPS61165054U
Application number: JP4951985U
Authority: JP
Priority date: 1985-04-03
Filing date: 1985-04-03
Publication date: 1986-10-13

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の構成図、第２図は
第１図における要部の動作を説明するタイムチヤ
ートである。３…直流電源、４…電源導入手段、５…第１出
力端子、６…第２出力端子、１０…電圧検出手段
、１１…第１ゲート手段としての第３制御リレー
、１３…論理演算手段、１４…第２ゲート手段、
１５…電源装置、Ｃ…コンデンサ、Ｘ_ａ１…第１
検出信号を形成するａ接点、Ｘ_ａ２…第２検出信
号を形成するａ接点、Ｙ_ａ１…第２制御信号を形
成するａ接点、Ｙ_ａ２…自己保持信号を形成する
自己保持接点、Ｙ_ｂ１…第１制御信号を形成する
ｂ接点、Ｔ_１…オフデイレー手段としてのオフデ
イレータイマ、Ｔ_１ａ…オフデイレー信号を形成
する限時ａ接点、Ｔ_２…オンデイレー手段として
のオンデイレータイマ、Ｔ_２ａ…オンデイレー信
号を形成する限時ａ接点。 FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart illustrating the operation of the main parts in FIG. 1. 3... DC power supply, 4... Power introduction means, 5... First output terminal, 6... Second output terminal, 10... Voltage detection means, 11... Third control relay as first gate means, 13... Logical operation means, 14...second gate means,
15...power supply device, C...capacitor, X _a1 ...first
A contact that forms a detection signal, X _a2 ... an a contact that forms a second detection signal, Y _a1 ... an a contact that forms a second control signal, Y _a2 ... a self-holding contact that forms a self-holding signal, Y _b1 ... B contact that forms the first control signal, T ₁ ... Off-delay timer as off-delay means, T _1a ... Time-limited a contact that forms off-delay signal, T ₂ ... On-delay timer as on-delay means, T _2a ... On-delay timer A time-limited a contact that forms a signal.

Claims

[Scope of utility model registration request]

a power introduction means for introducing a DC power; a capacitor charged by the DC power introduced through the power introduction means; first and second output terminals; a first detection signal and a second detection signal that are output when the voltage exceeds the input voltage and disappear when the voltage falls below a voltage lower than the input voltage; voltage detection means for outputting; off-delay means for outputting an off-delay signal that is output immediately when the first detection signal is input and disappears after a first set time has elapsed when the first detection signal disappears; a first gate means which, when inputted, is supplied with power by the charged charge of the capacitor and the DC power supply, and which leads the end voltage of the capacitor and the voltage of the DC power supply to the first output terminal; When the first control signal is input, the capacitor is supplied with electric charge and the DC power source supplies power to start a timekeeping operation, and after a second set time has elapsed from the start of the timekeeping operation, the off-delay signal and the second control signal are output. an on-delay means for outputting an on-delay signal that disappears when at least one of the one control signal disappears; at least one of the on-delay signal and the self-holding signal, and the second detection signal; When input, outputs a second control signal and the self-holding signal,
logical operation means that outputs the first control signal when both the on-delay signal and the self-holding signal disappear or when the second detection signal disappears; when the second control signal is input, the a second gate means for guiding the DC power introduced through the power introduction means to the second output terminal;
A power supply device comprising: a power supply device configured to output a DC voltage from each of the first output terminal and the second output terminal.