JPS61164237A - Multilayer probe card - Google Patents

Abstract

PURPOSE:To enable to reduce the pitch of pads by a method wherein a probe is separated into the lower layer probe and the upper layer probe, one end of the probes is electrically connected to the wiring conductor to be used for an electric test. CONSTITUTION:The lower probes 9 and 9' and the upper layer probes 8 and 8' are made of an insulating material 7 such as silicon resin and the like in double-layer structure. As the probes are formed in double-layer structure, it is necessary that the pitch of probe arrangement of the upper and the lower layers is set at approximately 150mum, and the pitch of pads can be changed to the pitch with which a bonding can be performed. As a result, the pitch of electrode terminals (pad) can be made small while the electric test technique and the size of the probes which were feretofore in use are being applied, thereby enabling to reduce the size of a semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a probe glove card used for electrical testing of semiconductor devices in a wafer state.

Normally, a plurality of semiconductor devices are formed on a single silicon substrate (wafer), and after diffusion and wiring processing are performed in the wafer shape, a probe is placed on the electrode terminal to perform an electrical characteristic test (electrical test). Thereafter, it is separated into individual semiconductor elements (semiconductor chips) by forming a depression with a laser beam or cutting with a thin diamond wheel, and those that pass the electrical test are placed in a container and the electrode terminals of the semiconductor elements and the leads of the container are connected.

The size and pitch of electrode terminals (pads) of a semiconductor device are determined by the following factors.

(1): Pad size is the size of the tip of the probe card from an electrical test perspective, and the alignment accuracy of the pad and tip when measuring continuously since multiple semiconductor elements are measured in a wafer. determined by In addition, the connection (bonding) between the leads of the container and the pads is determined by the lead bonding method, the manufacturing constraints of the leads, and the connection strength.

(2): From the standpoint of electrical testing, the pad pitch is determined by the pitch at which the probes on the glove card can be arranged.
It cannot be made smaller than the array pitch of the probes, and is limited by its size.

Also, from the viewpoint of bonding, pad spacing (clearance) is required so that adjacent pads and leads do not come into contact with each other due to plastic deformation of the pads and leads during bonding.

As is well known, the price of semiconductor devices is greatly affected by the size of the semiconductor chip, so various methods are being used, such as reducing the pad pitch and arranging the pads in multiple rows. and the array pitch, and the semiconductor chip size is increasingly constrained by the probe size and array pitch. As a result, with the large-scale integration of semiconductor devices, the size of a semiconductor chip tends to be determined by the number of pads, resulting in an increase in the price of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a probe card that can solve the above-mentioned drawbacks and reduce the pad pitch.

The present invention is characterized by a wiring conductor for electrical testing provided on one main surface of a printed circuit board having an opening larger than the semiconductor chip, and a wiring conductor that protrudes into the opening and has a tip facing the electrode terminal of the semiconductor chip. The probe is separated into a lower layer probe and an upper layer probe by an insulator, and one end of the probe is electrically connected to a wiring conductor for electrical testing. It is.

The present invention will be described in detail below using the drawings.

FIGS. 1A and 1B show a conventional probe card. In FIG. 1, the IC21 probe card board, 2 is a wiring conductor for electrical testing, 3 is a probe, 4 is an opening, 5 is a semiconductor substrate, 6 is a band, and 7 is an insulator such as silicone resin. Note that only a portion of the electrical test wiring conductor is shown and the rest are omitted.

The probe is fixed with an insulator such as silicone resin.

The electrical test is carried out by placing the probe 7 on the pad 6, but the probe needs to measure several dozen wafers or more for economic reasons, and it is important that the probe has high mechanical strength and high wear resistance. As required, the diameter of the probe is several tens of microns to 100 microns, and its tip is tapered.

In electrical testing, semiconductor devices are measured continuously, so the pad size is approximately 100 mm due to the alignment accuracy between the probe and the pad.
μ. Since the thickness of the probe needs to be several tens of microns to 100 microns in terms of mechanical strength and wear resistance, the pitch of the pads cannot be less than about 150 microns.

° FIG. 2(A) shows an embodiment of the present invention.

FIG. 2(B) is a top plan view of section A in FIG. 2(A).

In FIG. 2, 1 is the probe card board 9, 9' is the lower layer probe, 8, 8' is the -F layer probe, 5 is the semiconductor substrate, 6.6
．． 6.6 is a pad, and 7 is an insulator such as silicone resin. A two-layer structure of the probe can be easily achieved by fixing the lower probe with an insulator and then installing the upper probe on the insulator. Compared to conventional glove cards, the probe has a two-layer structure, so the probe array pitch in each of the upper and lower layers must be approximately 150μ or more, as in the past, but the pad pitch is set to a pitch that allows bonding. It is possible to do so. As a result, it is possible to reduce the pitch of the electrode terminals (pads) and reduce the size of the semiconductor chip while applying the conventional electrical test technology and probe size.

As described above, the present invention solves the restriction on the probe arrangement pitch of a probe card, which had prevented the reduction of the arrangement pitch of electrode terminals (pads), and the effect becomes more pronounced as the number of electrode terminals of a semiconductor device increases. Its industrial value is extremely large. In the embodiments of the present invention, the electrode terminals of the semiconductor element are arranged in one row, but the present invention is not limited to this arrangement, and a plurality of electrode terminals may be arranged. In the embodiment of the present invention, the probe of the glove card has a two-layer structure, but the present invention is not limited to this.

In short, it does not matter as long as the probe of the glove card has a multilayer structure.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are diagrams showing a conventional glove card. FIGS. 2(A) and 2(B) are diagrams showing an embodiment of the present invention. In the figure, 1... Probe card board,
=6-2...Wiring conductor for electrical test, 3...
Probe, 4...Aperture, 5...Semiconductor substrate, 6,6.6.6...Band, 7...
・Insulator, 8.8'... Upper layer probe, 9°9'・
...This is a lower level search button. Gi 5

Claims (1)

[Claims] A wiring conductor for electrical testing provided on one main surface of a probe card board having an opening larger than the semiconductor chip, and a probe protruding into the opening and provided at a position where the tip end faces the electrode terminal of the semiconductor chip. A multilayer probe comprising: a lower layer probe and an upper layer probe separated by an insulator; and one end of the probe is electrically connected to a wiring conductor for electrical testing. card.