JPS61163651A - Master-slice integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a master-slice IC device, through which a logic circuit in which the lowering of load driving capacitance with the increase of inputs is prevented can be realized, by reducing the number of elements required per the number of inputs and driving the whole outputs through a composite inversion buffer consisting of a bipolar and a CMOS. CONSTITUTION:The number of inputs to a cell 10 is increased only by NMOSFETs Q2c-Q2f. Since feed through currents are generated at that time, source-drain terminals 118, 119 for a PMOSFETQ1b for precharge, source-drain terminals 116, 117 for an NMOSFETQ2b for discharge and clock signal input terminals 103 are fitted, and currents are inputted to gates for the Q1, Q2, thus dynamic-operating a device. When the number of inputs is increased, the number of cascade connections of NMOSFETs is augmented and the resistance of input steps is elevated, thus reducing base currents in bipolar elements Q3a, Q3b at output steps. Consequently, the input steps and the output steps are separated, and the output steps are constituted by inverters, thus preventing effects. A logic circuit consisting of four inputs to the Q2c-Q2f can be constituted by selective connections, the logic circuit such as a NOR with a bipolar CMOS composite type inversion buffer is obtained, and only one is increased as elements.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application on N Beams) The present invention relates to a bipolar/0M0B composite master slice integrated circuit device that is small in size, has high operating speed, and has low power consumption.

(Summary of the Invention) The present invention provides a plurality of nM08FI! ! T, pM
Cells for realizing basic logic functions consisting of O8FKT and a group of two npn pieborad transistors are arranged in a play pattern on the same substrate in an unwired state, and predetermined circuit functions can be realized by post-processing wiring between the elements and between the cells. In the master slice integrated circuit device, there are at least one nMO8F1! whose gate electrode is connected to a signal input terminal. an input signal circuit of fT, first and second npn pipolar transistors connected in series, and the first
is connected in series between the collector and emitter of the npn bipolar transistor, pMo FET and nM08IF1!
iT, the connection point of both MOEIFFliTs and the base of the first transistor are connected, and the two nM08FIltTs are connected in cascade between the collector and emitter of the second npn bipolar transistor, and the two nM08FIltTs are connected to the base of the first transistor. Both nMO81FI! an output circuit which is fully connected between the connection point of iT and the base of the second transistor, and whose output terminal is the connection point between the emitter of the first transistor and the collector of the second transistor, and nM08F]I! ? and pM08PIl! Precharge and discharge circuits with T, one clock terminal, one power supply terminal and one
The number of elements required for each cell is reduced by providing two ground terminals for each cell, and the number of required elements is reduced relative to the number of inputs. This is designed to realize a dynamic logic circuit that can prevent the load driving ability from deteriorating in the classroom.

(Prior Art and Problems to be Solved by the Invention) A conventional device of this type had a cell configuration as shown in FIG. In FIG. 6, lO is a cell, 20 is a master slice integrated circuit device chip, 30 is a chip input/output circuit and terminals, 40 is a cell column, 50 is a wiring channel region, xo
l&-1o1b is a cell signal input terminal, 102 is a cell output terminal, 105 is a power supply terminal, 106 is a ground terminal,
111 and 112 are source or drain terminals of nMOSFETs for logic configuration, and 118 and 119 are p MOSFETs for logic configuration as well. ! The source or drain terminal of T, 130 and 131 are the drain of nMO8FIT for resistor replacement and the base terminal of npn bipolar transistor,
120 and 122 are gate terminals of nMO81FIT for resistor replacement, Q, la to QBbh logic configuration pM08PKT
, Ql@ ~Q*b is nM for logic configuration.

8FET, Q! O~Qll is nMo day F for resistor replacement
ET and Qsa to QNI are npn bipolar transistors. By making prescribed wiring between each terminal of these cell constituent elements, cell input/output terminal, power supply terminal, and ground terminal, the two cells are connected in a totem pole manner as shown in Figure 7 (a) and (b). A composite logic circuit can be constructed in which the output is driven by an npn bipolar transistor and the logic function is realized in an aMOB format. This type of circuit consumes no power in steady state, and its load driving ability is pure C! M
Since it is extremely large compared to O8K, the wiring capacitance load is large, making it possible to operate the master slice LSI at low power and high speed. However, as can be seen from FIG. 7, only logical functions that can be realized by two people can be realized using an l cell.

That is, in non-conventional devices, two complementary p-type and n-type transistors are used as input transistors to reduce power consumption and prevent through current.

Therefore, it is impossible to put more than two people into an l cell because it takes two people to put in the work based on the difference between the two conductivity types, p-type and n-type. In order to realize logic that requires more than three people's effort, it is necessary to use two or more cells, which has the disadvantage of reducing the degree of integration. The more inputs there are, the more MOS
As the number of cascade-connected FETs increases, the current flowing into the output stage npn bipolar transistor pace decreases.
This has the disadvantage that the load driving ability is reduced and the delay time is also significantly delayed.

(Means for Solving the Problems) The present invention was proposed to eliminate these drawbacks by reducing the number of required elements for the input circuit, and by using a composite inverting buffer of bipolar and cMOB for all outputs. It is an object of the present invention to provide a master slice integrated circuit device having a cell configuration capable of realizing a dynamic type logic circuit that can be driven through the input circuit and thereby prevent a decrease in load driving ability due to the input field. do.

The feature of the present invention is that nMO8FFIT01 rice is used and the number of inputs can be increased as desired.

In this way nM08FI! The problems to be solved when configuring the input transistor only with iT are (a)
When using both p-type and n-type MOSFETs, they cancel each other out and no through current occurs, but when only nMOSFETs are used, this occurs. To solve this problem, precharge,
Disjudge and clock terminals are provided to enable dynamic operation.

(b) As the number of inputs increases, the number of nMOSFETs connected in series increases, and as a result, the number of resistance valves in the input stage increases, so that the current flowing into the npn bipolar transistor in the output stage decreases. The solution to this problem is to separate the input stage and output stage and configure the output stage with an inverter so that it is not affected by the increase in the number of inputs.

(Example) Next, the present invention will be explained in detail. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 1 shows a first embodiment of the integrated circuit device of the present invention, in which QIIIL I Qf& is pM for supplying base current of bipolar transistors 'Lsa and Qlt+.
08F] IiT and nMO8FFiT, Q, b I Q
B. is precharge.

pM08FET and nMOSFET for discharge,
Ql.

~Qlf is nMO1111F1 for realizing logical function! :T
, 101a to 101d are signal input terminals, 103
is a clock signal input terminal, and 104 is Fl! fT Q+b
l Qtb gate terminals, 111-115 are nMO8
FI! ! TQ! +l s Q+ta l QCs I
Q, source or drain terminal of zf, 116-11
7 is the source or drain terminal of nMOBIP'ET for discharge, 118 to 119 are pM for precharge
OθFl! iT source or drain terminal, 121
, 123 are bipolar transistors Qlb + Q, respectively.
3a pace current supply puosFIT, nMO8
FF! The gate terminal of T, 124 is pM08 for supplying the collector and base current of the first NPN bipolar transistor.
F1! common terminal to the source of T Ql, 125 is the second
This is the emitter terminal of the npn bipolar transistor. With such a configuration, a dynamic logic circuit can be constructed by wiring between element terminals and cell input/output terminals, as shown in FIG.

nMO for configuring the logic circuit in Figure 3 (a)
SFETs Q,, ~Q, are connected in parallel to each other in 4
Configure a human powered NOR circuit. pMO8FFiT Ql is connected between one terminal a of this input signal circuit and the power supply line 105.
The source and drain of b are connected, and nMO8F]! is connected between the other terminal and the ground wire. ! TQ! ! , are connected, pMOIIiFInT Qtb and nMO81F! !
The clock signal input terminal 10 is connected to the gate terminal of TQ4B.
3 is connected. Also, one terminal a of the input signal circuit
The connection point between p M OB F I T Qt b and the drain thereof forms a node 200 .

Next, the operation will be explained.

When the clock signal on the clock signal input line 103 is at low level, pMOBFI! iT Q, tb is on, n
M.

8F'l! i'f' Since Qtb is off, node 2
00 is No1 Irepel. Next, if the clock signal is at no level, pMo day Fl! ! T Qtb is off,
nM08FFiT Since Q, b is on, nMO8
When a high level input signal is applied to any of the gates of FIT Ql6 to Q*t, this nMOSFET is turned on and the node 200 becomes low level. n M.O.
8FEiT QB. ~Q! When both gates of f are at a low level, the node 200 is also disconnected from the power supply and ground, and the high level is maintained by the capacitance of this node, so these circuits operate dynamically. npn/: Ibora transistor Q, al QB)
and pM08F1 connected to these paces, collectors and emitters! When node 200 is at high level due to the operation of iT and nMOEIFFIT, output terminal 1
02 is at a low level, and conversely, when the node 200 is at a low level, a voltage level appears at the output terminal 102, and the output terminal 102 functions as a so-called inverter.

In FIG. 3, Q. ~ Q pin nMOSFET is 4
Although it embodies human-powered NOR, if you change these connections, you can create various logical functions (NOR, ANII-NOR) powered by four people.

0R-NARD) can be realized. Multiple input logic circuits can be formed by increasing the number of nMOSFETs. The circuit shown in FIG. 3 is a 0M0B dynamic logic circuit with a bipolar 0M0B composite inverting buffer, and its feature is that the required number of elements per number of inputs is 1, so that the increase in the number of elements when multiple inputs is performed is small. Furthermore, the magnitude of the drain current of the MO87ET for pace current injection, which determines the drive ability of the bipolar transistor in the output stage, that is, the current supplied to the base of the bipolar transistor, is unrelated to the increase in the number of inputs. However, there is no change in load driving capacity. In other words, logic design becomes significantly easier.

FIG. 2 shows a second embodiment of the present invention, in which the ct of FIG.
,! gl Qth is replaced by resistor RItl l RI&, and the channel width/channel length ratio is different from other MO8.
FN! ! nMO8PFiT Q which is less than 1/10 of T
u and pMo day P1! iT qt. has been added. 1
26 and 127 are the source or drain terminals of Qllm'L1°, respectively.

In this case, nMO8F]I! T Q, 111 and nMO8
FEfT Q, *i # pMO8F'IT Q, 1b
and pMOEIF]! ;T It is connected to Q+a, but there is no particular need for it to be connected. If such a configuration is adopted, as shown in FIG. 3 (b), the precharge pMO
EIFKT Q,, in parallel with pMO8FKT Ql. Connect this MO8FFiT Q,,. By connecting the gate of K to the ground, when the information holding node 200 is at a high level, it becomes possible to maintain that level forever, and the present dynamic circuit can be changed into a synchronous static circuit. Also pMO8F]! iT
Q... The channel width/channel length ratio of
Since it is 1/10 or less of that of an IFET, the resistance between the source and drain of this FET can be increased to reduce the so-called through current flowing between the source and drain, thereby reducing power consumption. Also, as shown in Figure 4, D
Type latches can also be easily configured. In Figure 4, p
M08FF! T Q, t. and nMOI3FKT Q,
, , are used to configure a feedback inverter to permanently hold latched data. Furthermore, according to the present invention, a D-type latch, which required two or more cells in the conventional cell configuration, can be configured with one cell.

In the embodiment shown in Fig. 3, a four-person OR circuit can be realized with one cell, but in the conventional cell configuration, a four-person NOR (or O
R) Two cells are required to make the circuit. On the other hand, since the cell size of the present invention is 20 to 30% larger than the conventional cell size, the area can be reduced by about 40% using four-person logic.

FIG. 5 shows another embodiment of the present invention, in which nM
O8F1! ! By arranging a plurality of T's, even a multi-input logic that requires four or more people can be realized within one cell width by using these nMO8FIIIiTs.

In the embodiment of the present invention, nMO8I that realizes the logic function
Although the number of ETs is limited to four, this number does not determine the essence of the present invention.

Further, in the present invention, the first npn bipolar transistor Q3a for the output stage and the pMO transistor for supplying the pace current
SFET Ql, the pace of the former and the drain of the latter are shared, and the second npn bipolar transistor Q3
kl and its pace current supply n M087ETQ! If a manufacturing method and layout are adopted in which the collector of the former and the drain of the latter can be shared, the cell size can be further reduced.

(Effects of the Invention) As explained above, according to the present invention, the cell configuration is such that a compact, high-speed, low power consumption, multi-input logic circuit can be easily realized. - There are many products that have the effect of realizing a high-speed master slice LSI.

[Brief explanation of the drawing]

1 and 2 are examples of cell configurations according to the present invention, FIG. 3 is a bipolar 0M0E+ complex dynamic logic circuit that can be realized using the cell according to the present invention, and FIG. 4 is a type latch that can be realized using the cell according to the present invention. The circuit diagram, FIG. 5 shows another embodiment of the present invention, and FIG. 6 shows a conventional bipolar CMOB.
FIG. 7 is a diagram showing the chip configuration and cell configuration of a composite master slice semiconductor device, and shows a bipolar 0MO8 composite logic circuit that can be realized using conventional cells. lO... Cell, 20... Chip, 30... Chip input/output circuit and terminal, 40... Cell column, 50... Wiring channel region, 101a-10111... Signal input terminal, 102... ... Cell output terminal, 103 ... Clock input terminal, 104 ... Gate terminal of MO8FIT for precharge and discharge, 105 ... Power supply terminal, 106 ... Ground terminal, 111 to 117, 1
26-.-nMO8F]! Source or drain terminal of iT, 118, 119, 127 ・-pMO8FI
! Source or drain terminal of iT, 120, 122
... nM087F for resistor replacement! T gate terminal, 121
... nMOSFET gate terminal for base current supply, 123 ... pMOSFET gate terminal for pace current supply, 124 ... output stage power supply terminal, 125 ...
Output stage ground terminal, 130, 131...npn
Transistor base terminal, 200... node, Q1&
. QIt+...9MO8FF, T%Q□~Q2g...
8MO8FET, Q3...npn bipolar transistor, RIll l RII)...Resistance Applicant Figure 5

Claims (4)

[Claims] (1) Multiple nMOSFETs and pMOSFETs each
and a master slice in which cells for realizing basic logic functions consisting of a group of npn bipolar transistors are arranged in an array on the same substrate in an unwired state, and a predetermined circuit function can be realized by post-processing wiring between the elements and between the cells. In an integrated circuit device, an input signal circuit consisting of at least one or more nMOSFETs whose gate electrodes are connected to signal input terminals, first and second npn bipolar transistors connected in series, and the above-mentioned A pMOSFET, an nMOSFET, and both of the above-mentioned MOS
The connection point of the FET is connected to the base of the first transistor, and the two npn bipolar transistors are connected in cascade between the collector and emitter of the second npn bipolar transistor.
an output circuit that connects a MOSFET, a connection point between both of the nMOSFETs and a base of a second transistor, and has an output terminal that connects the emitter of the first transistor and the collector of the second transistor; , nMOSF
1. A master slice integrated circuit device, wherein each cell includes a precharge/discharge circuit having an ET and a pMOSFET, one clock terminal, one power supply terminal, and one ground terminal. (2) The master slice integrated circuit device according to claim 1, wherein a resistor is connected between the base terminal and emitter terminal of the first and second npn bipolar transistors. (3) The channel width to channel length ratio of at least one pMOSFET and at least one nMOSFET is different from that of other pMOSFETs.
1/10 compared to MOSFET and nMOSFET
A master slice integrated circuit device according to claim 1, characterized in that: (4) Multiple nMOSFETs and pMOSFETs each
and a master slice in which cells for realizing basic logic functions consisting of a group of npn bipolar transistors are arranged in an array on the same substrate in an unwired state, and a predetermined circuit function can be realized by post-processing wiring between the elements and between the cells. In an integrated circuit device, an input signal circuit consisting of at least one or more nMOSFETs whose gate electrodes are connected to signal input terminals, first and second npn bipolar transistors connected in series, and the above-mentioned A pMOSFET, an nMOSFET, and both of the above-mentioned MOS
The connection point of the FET is connected to the base of the first transistor, and the two npn bipolar transistors are connected in cascade between the collector and emitter of the second npn bipolar transistor.
an output circuit that connects a MOSFET, a connection point between both of the nMOSFETs and a base of a second transistor, and has an output terminal that connects the emitter of the first transistor and the collector of the second transistor; , nMOSF
A plurality of nMOSFETs are arranged in gaps between cell rows each having a precharge/discharge circuit having an ET and a pMOSFET, one clock terminal, one power supply terminal, and one ground terminal. A master slice integrated circuit device characterized by: