JPS61162139U - - Google Patents

Info

Publication number
JPS61162139U
JPS61162139U JP1985044890U JP4489085U JPS61162139U JP S61162139 U JPS61162139 U JP S61162139U JP 1985044890 U JP1985044890 U JP 1985044890U JP 4489085 U JP4489085 U JP 4489085U JP S61162139 U JPS61162139 U JP S61162139U
Authority
JP
Japan
Prior art keywords
counter
count value
output
conduction
cutoff
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985044890U
Other languages
English (en)
Other versions
JPH0241953Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985044890U priority Critical patent/JPH0241953Y2/ja
Priority to US06/844,478 priority patent/US4691330A/en
Publication of JPS61162139U publication Critical patent/JPS61162139U/ja
Application granted granted Critical
Publication of JPH0241953Y2 publication Critical patent/JPH0241953Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K11/00—Transforming types of modulations, e.g. position-modulated pulses into duration-modulated pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Feedback Control In General (AREA)
  • Dc-Dc Converters (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
  • Arrangements Of Lighting Devices For Vehicle Interiors, Mounting And Supporting Thereof, Circuits Therefore (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例の回路構成図、第２
図ａは室内ランプの明るさの時間的変化を示した
図、第２図ｂはランプ電流のデユーテイ変化の状
態を示した図である。 図面中、１は第１のカウンタ、２は第２のカウ
ンタ、３は第３のカウンタ、４はマグニチユード
コンパレータ、５はラツチ回路である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 導通と遮断のデユーテイの逓減率ｉ／ｎ（ｉ＝
    １、２…ｎ）を決定する。第１のｎ進カウンタと
    、該第１のカウンタの計数値ｎの出力をｍ回計数
    する第２のｍ進カウンタと、該第２のカウンタの
    計数値ｍの出力を入力して歩進される第３のカウ
    ンタと、上記第１のカウンタの出力と第３のカウ
    ンタの計数値を比較し、第１のカウンタ計数値が
    第３のカウンタの計数値に等しいか大きい間、上
    記導通に対応するレベルの出力信号と、第１のカ
    ウンタ計数値が第３のカウンタの計数値より小さ
    い間、上記遮断に対応するレベルの出力信号とを
    出すマグニチユードコンパレータからなることを
    特徴とするデユーテイ制御回路。
JP1985044890U 1985-03-29 1985-03-29 Expired JPH0241953Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1985044890U JPH0241953Y2 (ja) 1985-03-29 1985-03-29
US06/844,478 US4691330A (en) 1985-03-29 1986-03-26 Duty control circuit for gradually reducing the duty time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985044890U JPH0241953Y2 (ja) 1985-03-29 1985-03-29

Publications (2)

Publication Number Publication Date
JPS61162139U true JPS61162139U (ja) 1986-10-07
JPH0241953Y2 JPH0241953Y2 (ja) 1990-11-08

Family

ID=12704076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985044890U Expired JPH0241953Y2 (ja) 1985-03-29 1985-03-29

Country Status (2)

Country Link
US (1) US4691330A (ja)
JP (1) JPH0241953Y2 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164969A (en) * 1991-07-12 1992-11-17 Hewlett-Packard Company Programmable max/min counter for performance analysis of computer systems
US5420467A (en) * 1992-01-31 1995-05-30 International Business Machines Corporation Programmable delay clock chopper/stretcher with fast recovery
JP3333248B2 (ja) * 1992-11-10 2002-10-15 株式会社東芝 デューティ検出回路
US5534733A (en) * 1993-06-25 1996-07-09 Meg Trans Corp. Digital dimming and flashing circuit for locomotive ditch lights
US5479125A (en) * 1994-05-25 1995-12-26 Zilog, Inc. Frequency multiplying clock signal generator
JP3696077B2 (ja) * 2000-11-13 2005-09-14 シャープ株式会社 電圧変換回路及びこれを備えた半導体集積回路装置
US8717067B2 (en) * 2005-02-28 2014-05-06 Agere Systems Llc Method and apparatus for continuous-averaging counter-based digital frequency lock detector

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4396869A (en) * 1979-03-05 1983-08-02 Leviton Manufacturing Company, Inc. Time responsive variable voltage power supply
US4408142A (en) * 1981-05-20 1983-10-04 Wilje Sven O E Device for the control of the luminous flux from a main beam bulb in a motor vehicle

Also Published As

Publication number Publication date
JPH0241953Y2 (ja) 1990-11-08
US4691330A (en) 1987-09-01

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