JPS61161872A - Video signal digital encoding and decoding system and device for memory reproducing - Google Patents

Abstract

PURPOSE:To obtain inexpensively a video signal encoded by 1-bit-time-series digital encoding by forming a loop system with an analogue-signal comparing circuit, temporary memory circuit, and a high-pass-filter circuit. CONSTITUTION:The input video signal to be encoded is inputted to an analogue- signal comparing circuit 104 from the input terminal 1. The output from the circuit 104 is synchronous with the synchronizing signal 107 from a reference clock generator 201, and is stored in the temporary memory circuit 106. From the memory circuit 106, an encoded video signal 108 is outputted, which is supplied to a memory control circuit 203 and to a first filter circuit 109 that is of high-pass characteristic. The output from the circuit 109 is supplied to the comparing circuit 104, and thus the loop is formed. By this constitution of the loop, a digital-encoded video signal of 1-bit time series is obtained without frame memory.

Description

[Detailed Description of the Invention] This invention relates to a digital encoding method and demodulation method for storing and reproducing video signals.It is capable of directly encoding composite video signals, whether monochromatic or color, and is less expensive than conventional methods. It is characterized by its cost.

Video signal encoding usually uses a 6-bit to 8-bit ultra-high-speed analog-to-digital converter (hereinafter referred to as ADC).
Digital analog converter (hereinafter referred to as DAC)
is used. Video signal is generally 5MHz
It is necessary to reproduce a frequency band of about 10 MHz.

For this reason, the operating speed performance required of ADCs and DACs is severe, and as the number of bits increases, the cost becomes extremely high.

In recent years, video-related devices have become popular and costs have been reduced, but the cost of video storage and playback devices commonly referred to as frame memories is high for the reasons mentioned above.

Theoretically, the video signal contains a DC component, so O
Reproduction characteristics from HZ are required. This may be inconvenient when configuring an actual circuit, so by providing a section near each horizontal synchronization signal that determines the reference brightness for that horizontal scanning period, the video signal circuit system can be configured with a complete DC amplifier circuit. The six proposed proposals that are free from this problem are 1-bit time-series encoding methods for video signals and demodulation methods thereof, which focus on this point. Details will be explained below using the drawings.

FIG. 1 is a block diagram showing an example of the basic configuration of the present invention. 1
01 is an input terminal for the video signal to be encoded, 102
is the next 104 analog signal comparison circuit 2 of that signal.
One of the book's input lines, 103, is the other input line.

105 is the output of the analog signal comparison circuit, and 106 is a temporary storage circuit that temporarily stores the state in synchronization with the synchronization pulse 107. 108 is its output, and this signal will be referred to as an encoded video signal in the following explanation. Reference numeral 109 denotes a first filtering circuit that filters the encoded video signal with high-frequency cutoff characteristics.

This output 103 becomes one input of an analog signal comparison circuit 104. This signal will be referred to as a coded demodulation feedback signal in the following explanation.

Reference numeral 201 is a reference clock generation circuit that generates a reference clock necessary to operate the entire system. 202 provides a synchronizing pulse to the encoding system 107 and a clock to the memory control circuit 202; A memory control circuit 203 controls writing the encoded video signal to the memory and reading data from the memory. 204 is a control signal line for memory, and 205 is the memory.

206 is a horizontal synchronizing signal input, and 207 is a vertical synchronizing signal input, each of which is used to initialize the state of the system.

301 is a readout signal of the encoded video signal on the memory. 302 has the same or similar characteristics as 109.
It is a filter circuit. 303 is its output, which will be referred to as a reproduced video signal in the following explanation. 304 is its output terminal.

A second initial setting circuit 401 receives a horizontal synchronizing signal and determines the initial state of the second filter circuit. 402 is its control line.

A loop system consisting of an analog signal comparison circuit 104, a temporary storage circuit 106, and a first filter circuit 109 constitutes the encoding method described in claim 1.The operation of this system will be explained below. do. The operation of this system proceeds in such a way that the signal 103 follows the signal 102. The situation will be explained using Fig. 2. The horizontal axis is the time axis, and the vertical axis is the magnitude of each signal waveform.The line at 0 time t=φ is the start time of the explanation. 1 is the video input signal waveform on 102 in FIG. This waveform is different from the exact video signal waveform, and has been simplified to simplify the explanation, but this has nothing to do with the essence of the case. 102 from 101 indicates the horizontal synchronizing signal section, 2 indicates the video signal It has the same waveform as the input signal. 3 is a coded demodulation feedback signal 103 in FIG. 4 is the encoded video signal 108 in FIG. 5 is 107
This is the synchronization pulse above. To make the explanation easier to understand, the interval between synchronizing pulses is set larger than that generated in the actual circuit.Assuming that 2 and 3 are the same value at time t; φ and the output state of the temporary storage circuit is φ, the high frequency cutoff The first with characteristics
The output of the filter circuit continues to fall and is completely below the input video signal at the time of the next sync pulse. Therefore, at this time, the output of the comparison circuit is in the 1 state, and as a result, the output of the temporary storage circuit, that is, the waveform of 4, is in the 1 state. As a result, the output of the first filter circuit starts to rise at time t2 in Figure 0.
Since it exceeds the input video signal at the time of the synchronization pulse, it is reversed at this point. In this way, the output of the first filter circuit follows the input video signal, albeit in a zigzag manner. In the actual circuit, the interval between synchronization pulses is very short, and the tracking speed of the first filter circuit is faster than shown in the diagram, so the output of the first filter circuit becomes a fine zigzag waveform as shown in Figure 2 (6), and the input video signal I follow it completely. In the following description, the difference between the input video signal and the coded demodulated feedback signal will be referred to as a coding error. As for the characteristics of the first filter circuit, a double integration circuit is effective, but in general, it is necessary to have high-frequency cutoff characteristics, and the specific characteristics are the essence of this proposal. Since this is not the place to do so, detailed explanation will be omitted. In order to simplify the explanation, the example in FIG. 2 shows the case where the first filter circuit is a single integration circuit. 1 filter circuit characteristics and the unique properties determined by the synchronization of the synchronization pulses. Here, since the input video signal and the encoded demodulated feedback signal are equal, the encoded video signal, that is, the output of the temporary storage circuit is a 1-bit time-series encoded signal of the input video signal. In a general amplitude-pulse width modulation circuit, the pulse time width is extracted as an analog quantity, but the present invention is characterized in that the pulse time width is extracted as a digital quantity.

The detailed operations mainly related to memory from 201 to 207 in FIG. Therefore, detailed explanation will be omitted.

The second filter circuit 302 constitutes the demodulation method described in claim 2. The input to the second filter circuit, that is, the memory readout signal, has a waveform similar to the encoded video signal 4 in FIG. 2. Therefore, the characteristics of the second filter circuit should be made equal to the characteristics of the first filter circuit. Accordingly, the output of the second filter circuit, that is, the reproduced video signal waveform, becomes equal to the output of the first filter circuit, that is, the encoded demodulated feedback signal. As a result, the reproduced video signal has a waveform similar to the input video signal except for encoding errors.

A second initial setting circuit 401 sets the electrical initial state of the first filter circuit as described in claim 3. This timing is done by a horizontal synchronization signal. The reason why this initial setting circuit is necessary will be explained.

Figure 3 shows an example of a reproduced video signal without an initial setting circuit. 1, 2, 3, and 4 are horizontal synchronization signal parts, respectively. One drawback of the encoding method according to the present invention is that there is a steady deviation in the reproduced signal. may occur. i.e. 11.21
．． 0, which is the difference from the expected reference level of 3141. Normal video-related equipment is equipped with a function to initialize the reference level near each horizontal synchronization signal so that it is not affected by this difference. There are few cases where an initial setting circuit is required. However, if this type of reference level fluctuation is not allowed for a single device, it is possible to define the initial value of the second filter circuit at the timing of horizontal synchronization. This fluctuation can be suppressed. This level fluctuation is caused by the fact that the first filter circuit generally has integral characteristics. That is, obtained by this encoding system
The encoded signal corresponds to the input video signal with a differential characteristic that is conjugate to the integral characteristic of the first filter circuit. When this encoded signal is demodulated by a second filter circuit having an integral characteristic, the encoding error and the demodulation error are integrated and a long-period steady deviation occurs. However, in the case of an actual circuit, the steady-state deviation is caused by a constant effect due to saturation, and if the integral characteristic of the second filter circuit deviates from the midpoint potential, a slight heat loss is caused, so that a large steady-state deviation does not occur. be able to.

These properties naturally accompany the creation of an actual circuit even if they are not specially provided.

As explained above, the basic configuration of the present invention is as follows: A 1-bit time-series digitally encoded video signal can be obtained.

Furthermore, the original video signal can be reproduced by passing the encoded signal through one high-pass filter circuit.

With the method of the present invention, the encoding circuit and reproducing circuit can be simplified and realized at low cost compared to conventional methods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the basic configuration of the present invention. FIG. 2 is a diagram for explaining the operating state of each part in FIG. 1. FIG. 3 is a diagram for explaining the reason why the second initial setting circuit is necessary.纂目'1y37j! lN

Claims (1)

[Claims] 1) An analog signal comparison circuit, a temporary storage circuit that temporarily stores its output in synchronization with a synchronization pulse, and a first filter that receives the output of the temporary storage circuit and has high-frequency cutoff characteristics. a circuit in which the output of the first filtering circuit is connected to one of the two inputs of the analog signal comparison circuit, and a video signal to be digitally encoded is connected to the other input; A video signal digital encoding system characterized in that a 1-bit time-series digital encoded signal synchronized with the synchronization pulse is obtained from the output of the temporary storage circuit comprising: 2) The delayed signal or the stored and reproduced signal of the 1-bit time-series digital encoded signal obtained by the video signal digital encoding method as explained in the scope of claim 1 above is
It is characterized by having a second filtering circuit that cuts off high frequencies with a filtering circuit having the same or similar characteristics as the first filtering circuit described in section 1, and obtaining a reproduced video signal from the output of the second filtering circuit. A coded video signal demodulation method that uses 3) It is characterized by having the circuit as described in the second claim above, and a circuit for setting the electrical initial state of the second filter circuit in synchronization with the horizontal synchronization signal of the video signal. Coded video signal demodulation method. 4) It includes the video signal digital encoding method as described in the claim of item 1 above, and the encoded video signal demodulation method as described in the claim of item 2 or 3 above. Featured video signal storage and playback device