JPS61161824A - Precharge circuit - Google Patents

Abstract

PURPOSE:To cut off a precharge current in high speed by allowing an output circuit itself or a sense circuit to detect a bus potential and feeding back the output to a control input of a precharge switch. CONSTITUTION:When a selected internal data is logical 1 with a clock phi at L level, an electric charge of a data bus line 1 is drawn and a level of an output A of an output circuit 23 is logical L. In this case, an NMOS transistor (MOST)21 and a PMOST18 are turned off, an NMOST20 is turned on and a base B of an NPN bipolar transistor (BiT)17 is pulled down. When the clock phigoes to H in this state, the PMOST18 is turned on, the NMOST20 is turned off, a collector current of a switching element NPNBiT17 flows to charge the data bus line 1 to increase the potential. When the potential rise is increased, the conductance of the NMOST21 is increased, the base current of the NPNBiT 17 is decreased to be turned off thereby cutting off the precharge current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a dynamic bus such as a microprocessor or a memory, and particularly relates to a precharge circuit suitable for accessing a path at high speed.

[Background of the invention]

Figure 2 is a diagram showing a conventional precharge circuit (Japanese Unexamined Patent Publication No. 58
In Figure 2, 1 is a data bus line, 2 is a P-channel type MO8h
Ranjistor (hereinafter abbreviated as PH10).

3.4 is an N-channel MOS transistor (hereinafter referred to as NM
(abbreviated as O8T), 5, 6, 7.8 are inverter circuits, 9
is a capacitor, 10 is a NAND circuit, 11 is a precharge circuit for data bus line 1, 12 is a discharge circuit that outputs data to data bus line 1, 13 is an output circuit that reads data using the potential of data bus line 1,
14 is a level detection circuit that detects a predetermined potential of the data bus line 1;

15 is a Lt delay circuit, and 16 is a synchronous circuit.

FIG. 3 is a time chart showing the operation of the circuit of FIG. 2. The synchronization circuit 11 starts charging the data bus line 1 in synchronization with the clock φ.

When the potential of the data bus line 1 exceeds the detection level V of the level detection circuit 14, the level detection circuit 14 performs a detection operation and stops charging the data bus line 1 after a delay time by the delay circuit 15.

The discharge circuit 12 operates in synchronization with the discharge circuit T. When the internal data is "1", NN05T 4 turns on, extracts the charge from data bus line l, and the potential of data bus line l reaches the threshold level v1 of output circuitry 3.
When it becomes below, the output d rises. On the other hand, when the internal data is rOJ, NN08T3 is turned off, the potential of the data bus line E does not change, and the output d is also L (L
OW) level.

By the way, since the data bus line 1 generally has a wiring length of several square meters, it has a large parasitic capacitance. On the other hand, the NN08T3.4 is small in size for high integration, and has a large on-resistance, so that the charge stored in the data bus line 1 is discharged with an extremely large time constant. This results in a disadvantage that the data access time becomes longer.

It is determined by the time t1 when the potential of the data bus line 1 reaches the threshold level v1 of the output circuit 13.

FIG. 4 shows the input/output characteristics of the 0MO5 logic gate.

In general, a voltage v1. The logical threshold voltage v&? 8th 5a called
W is a diagram showing the relationship between path potential and delay time t4 when reading a path, and is the result of precharging.

When the initial voltage of the bus in a read cycle is set to V, the bus potential vh is expressed as −(t/c, b−Ra ,) V, TomiVh@e...(1)
The delay time t4 is.

It can be approximated by As shown in FIG. 2, after the level detection circuit 14 detects a predetermined path potential, the PMO8T2
is turned off and the bus is precharged to a sufficiently high potential, ta naturally increases.For example, the initial voltage of the bus v1. 4 (V), the logic threshold voltage V&? 2
(v), the delay time t4 is approximately 0.7τ, (τa=
C, -R, , : time constant of the discharge circuit).

That is, in order to read the bus at high speed, the precharge voltage v1
．． The logical threshold voltage v, ? It is necessary to bring the bus potential close to the above-mentioned logical threshold voltage V&? during precharging. After reaching PFIO for precharging
The delay time until 5T 2 is turned off must be reduced. Also, in order to speed up the bus access cycle, it is necessary to increase the precharge current, and in this case, it is necessary to increase the precharge current. However, in the conventional method as shown in FIG.

These cannot be satisfied.

[Objective of the invention]

An object of the present invention is to provide a precharge circuit that allows high-speed access to a dynamic bus.

[Summary of the invention]

In order to access the dynamic bus at high speed, it is necessary to increase the precharge current and turn off the precharge current quickly when the bus potential exceeds the logic threshold voltage of the output circuit. The feature is that the bus potential is detected by the output circuit itself for reading from the bus, or by a sense circuit that has logic threshold voltage matching with the output circuit, and the output of any of these circuits is used to detect the bus potential. The switching element that supplies the precharge current is controlled, and a high-speed feedback circuit is connected between the bus line and the control input of the switching element to quickly cut off the precharge current.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG.
NBiτ) 17 has its collector connected to the power supply voltage v6° and its emitter connected to the data bus line 1. One end of the series circuit of PMO5τ19 whose gate is connected to the output A of the output circuit 23 for reading data on data bus line 1 consisting of a series circuit of inverter circuits 21° and 22 and PMO5τ18 whose gate is controlled by clock φ is connected to the power supply voltage v0°. To.

The other end is connected to base B of NPNBiT 17.

NHO3T21 with gate connected to data bus line 1
NHO5T 20 whose gate is controlled by clock T and
One end of the parallel circuit is connected to the base B of NPNBiTl7, and the other end is connected to the ground.This embodiment will be explained using the time chart shown in FIG.

In the previous cycle (clock T is at high level), if the selected internal data is "1", the charge on data bus line 1 is drawn in and the potential on data bus line 1 is lowered, so the output circuit The output A of 23 is at low level. Therefore, PH08T19 is in the on state. On the other hand, NHO3T21 is in an off state because the potential of data bus line 1 is low, or.

is in a high impedance state. When the clock φ is at high level, PMO571B is off, NHO8T20 is on, and the base B of NPNBiTl7 is N
It is pulled down to ground by HO8T 20 . From this state, when the clock 7 is switched to low level, the PMO 8718 is turned on, the NMOST 20 is turned off, and the base BAPM of the NPNBiT 17 is turned on.
Current is injected through O5τ18.19. That is, PMO8T 18 and NHO8T 20 form a switching circuit that switches on/off cycles of NPNBiTl 7, which is a switching element. As a result, the collector current of NPNBiTl7 flows, charging the data bus line 1 and increasing the potential. By the way, when the potential of data bus line 1 rises, NHO8T21
As the gate voltage increases, the conductance increases, making it easier for current to flow. Therefore, P has 05T18
．． Since the base current that was flowing into NPNBiTl 7 is shunted and flows to NHO8T21, the potential of data bus line 1 changes to output circuit 23.
When it exceeds the threshold level vIl of
In order to extract the charge accumulated in the base B of NBiTl7, charging of the data bus line 1 is stopped.

That is, NMO5T21 is an output circuit 23. which detects the potential of the bus line. Compared to a control loop that controls the NPNBiT 17, which is a switching element, through this switching circuit, a high-speed feedback circuit is formed that feeds back the bus potential to the base of the NPNBiTl 7, which is the control λ power of the switching element, at a high speed. In this case, the precharge voltage vP of the data bus line 1 is equal to the voltage corresponding to the amount of charge charged between the response delay of the output circuit 23 and the operation delay of PNO5T19,N O5τ20.
The threshold level V of , becomes higher. However, in this circuit, as the voltage of data bus line 1 increases, NM
Since the charging current decreases due to the action of O5T 21,
The precharge voltage V of the data bus line 1 can be set to a level slightly higher than the threshold ILL/bell v0 of the output circuit 23.

That is, since the charging of the data bus line 1 is controlled by the output A of the output circuit 23, the charging of the data bus line 1 is controlled by the output A of the output circuit 23.
The relationship between the precharge voltage v2 and the threshold level V of the output circuit 23 is not affected by variations in elements, ambient temperature, power supply voltage, etc., and allows extremely stable operation. Furthermore, in this embodiment, the data bus line 1 is charged using a bipolar transistor having a high load driving capability, and the data bus line 1 is precharged with a sufficiently large precharge current, so that the precharge time can be shortened.

Moreover, the bus potential is the logic threshold voltage v& of the output circuit 23.
? When approaching , the precharge current is suppressed by the action of NN03T21 forming a high-speed feedback circuit, so that NPNBiTl 7 from the output circuit 23 is controlled with high precision. This results in, for example, a logic threshold voltage V&? =2
(v), if the precharge voltage Va of bus line 1 is set to 2.2 (V), then the read delay time t, from equation (2), becomes ta "0.095τ, which means that it is extremely fast. Allow bus access.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. The difference in FIG. 5 from FIG. 1 is that the gate is connected to the output circuit 2.
A series circuit of PMO3T25 connected to the output A of 3 and PMO8τ24 whose gate is controlled by clock φ has one end connected to the power supply voltage V. . The other end is connected to data bus line 1. PMO8T 24.

25 series circuit charges the data bus line 1 until the output A of the output circuit 23 is inverted. That is, in this embodiment, charging of the data bus line 1 is performed by a parallel circuit of the NPNBiT 17 and the series circuit of PMO8T24 and 25. Comparing the conductance of a bipolar transistor and a MOS transistor, the bipolar transistor is generally an order of magnitude larger, so the NPNBi
The charging current of Tl7 is larger than the charging current of the series circuit of PMO8T24.25, but as mentioned above, NPNB
The charging current of iTl 7 decreases as the potential of data bus line 1 increases. On the other hand, PMO5T24,2
The charging current of the series circuit of 5 is PMO5T24,2
Since it is determined by the conductance of the series circuit 5, it remains approximately constant even if the potential of the data bus line 1 changes. That is, PH03T 24 .

The 25 series circuits set the lowest value of the charging current for the data bus line 1, and can shorten the time for precharging the data bus line 1.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. What is different in Fig. 6 from Fig. 5?

Inverter circuit 21' to the gate of PMO5τ19.25
22' is connected to the output A' of a sense circuit 23' for detecting the bus potential, which is made up of a series circuit. The logic threshold voltage V& of the sense circuit 23' and the output circuit 23
? In this embodiment, a sense circuit 23' is provided separately from the output circuit 23, and its output A' provides the same circuit characteristics as the second embodiment. By controlling the charging of the data bus line 1, the degree of freedom in arranging the precharge circuit and the output circuit 23 of the data bus line 1 is increased, and the layout becomes easy.

A plurality of successive circuits 23 can be connected to the bus line 1, and the degree of freedom in system design is expanded.

FIG. 9 is a circuit diagram showing a fourth embodiment of the present invention. In Figure 9, a high-speed feedback circuit is added to NMO5T21, and P
Formed by a series circuit of MO5T26 and 27, PMO8
The gate of PMO5T27 is connected to the clock T to perform precharge cycle switching, and the gate of PMO5T27 is connected to bus line 1 to feed back the bus potential to NPNBiT 17 at high speed in the same way as NN05T21.

In this embodiment, an inverter amplifier is formed by NMO3T21 and PMO3τ27, and high-speed feedback to NPNBiT 17 is more optimally performed by eliminating the drawback that excessive braking is likely to occur when using only NN05T21.

FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.

What is new in the embodiment of FIG. 10 is that PMO5T28.29
Connect the series circuit of N803-30.31 in series, connect the connection point to bus line 1, and connect PMO5.
T 29 , the gate of NMO3T 31 is connected to bus line 1
In addition, the gate of PMO8τ28 is connected to clock T, and N
Add a circuit connecting the gate of MO3T30 to clock φ. PMO5T29, NMO3'f
31 forms an inverter amplifier, and both the input and output of this inverter amplifier are connected to the bus line 1. P.M.O.
5T28 and NMO3T30 set the logic threshold voltage of the inverter amplifier to be approximately equal to the logic threshold voltage of the output circuit 23, which performs switching to activate the inverter amplifier as a precharge amplifier.

The effect of this embodiment is that the inverter amplifier forms a precharge circuit with a small driving force but an independent minor loop, and the bus potential is set to the logic threshold voltage v&? It is to have a local path potential correction operation when there is a slight change from . That is, FIG.

The precharge circuits according to the embodiments shown in FIGS. 7, 8, and 9 form a kind of peak hold circuit. Therefore, the output circuit 23. Alternatively, if the potential of the bus line 1 gradually rises due to charge sharing with the discharge circuit 12 or the like, or due to leakage current, etc., no function is provided to lower the bus potential except for the discharge circuit 2.

In this embodiment, this function is added to the precharge circuit, and in addition to the supply of precharge current by NPNBiTl 7, an auxiliary precharge circuit is added to supply precharge current auxiliary.

〔Effect of the invention〕

According to the present invention, it is possible to set a precharge voltage that closely matches the logic threshold voltage of the output circuit without being influenced by the power supply voltage or the like.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional data bus line precharge circuit, and FIG. 3 is a time chart showing the operation of the circuit in FIG. 2. , 4y1 is a time chart showing the operation of the circuit in FIG. 1, FIG. 5 is a circuit diagram showing the second embodiment of the present invention, and FIG. 6 is a circuit diagram showing the third embodiment of the present invention. 7 to 10 are circuit diagrams of fourth to seventh embodiments of the present invention, respectively. 1... Data bus line, 17... NPNBiT,
18゜19.24,25...PMO3T, 20,2
1...NMO5T, 23... Output circuit.

Claims (1)

[Claims] 1. A precharge circuit that precharges a bus line;
In a dynamic bus line system consisting of an output circuit that reads data on the bus line and a discharge circuit that outputs data to the bus line, the bus line has logic threshold voltage matching with the output circuit or the output circuit; a sense circuit connected to,
controlled by the output of the output circuit or the sense circuit,
A precharge circuit comprising: a switching element connected between a first power source and the bus line; and a high-speed feedback circuit connected between the bus line and a control input of the switching element. 2. In claim 1, the switching element is a first conductivity type MOS transistor having a source connected to a first power supply, a drain connected to the bus line, and a gate serving as the control input. A pre-charge circuit characterized by: 3. Claim 1 provides that the switching element is a bipolar transistor of a first conductivity type, the collector of which is connected to the first power supply, the emitter of which is connected to the bus line, and the base of which is the control input. Features a pre-charge circuit. 4. In claim 1, the high-speed feedback circuit is of a first conductivity type and has a drain connected to the control input of the switching element, a source connected to the second power supply, and a gate connected to the bus line. A precharge circuit characterized by being a MOS transistor. 5. In claim 1, the high-speed feedback circuit comprises a first MO of a first conductivity type, the source of which is connected to a second power supply, and the drain of which is connected to a control input of the switching element.
S transistor, second and third MOS transistors of a second conductivity type connected in series between the first power source and the control input of the switching element;
A precharge circuit characterized in that a gate of an OS transistor is connected to the bus line and a gate of the third MOS transistor is connected to a clock input. 6. In claim 1, the bus line includes a fourth MOS transistor of a second conductivity type whose gate and drain are connected to the bus line, and a fourth MOS transistor whose gate and drain are similarly connected to the bus line. a fifth MOS transistor of one conductivity type; a sixth MOS transistor of a second conductivity type connected between the fourth MOS transistor and the first power supply;
A precharge circuit comprising: a transistor; and a seventh MOS transistor of a first conductivity type connected between the fifth MOS transistor and a second power supply.