JPS61161559A - Microcomputer - Google Patents

Abstract

PURPOSE:To use effectively an EPROM by limiting the access to the EPROM to one of plurally divided parts of memory capacity, and allocating selectively one divided area to one of plurally divided parts of the memory on an address. CONSTITUTION:Address signals a0-a12 from a control circuit 1 and the output of an OR gate 7 are given to an address decoder 3, and one address on an EPROM2 is selected by the address decoder 3. If the address exceeds 4k when 4k-number of bytes are selected, a NAND gate 13 reports it to the control circuit 1 that the address exceeds 4k, and the output of the EPROM2 is stopped.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a micro combinator made of a semiconductor integrated circuit, and particularly to a read-only memory (hereinafter referred to as BFROM) that can be written to, erased from, and read from a program memory. Concerning the built-in nine micro combinators. .

[Conventional technology]

In recent years, due to advances in semiconductor manufacturing technology, microcombi-
As the capacity of the built-in EFROM for storing programs increases, the internal R and OM used for program evaluation of the micro combinator or for small-scale production will become EFR.
For example, OM products are EFROM of about 8 bytes.
Capacity ones are also commercialized. However, depending on the application field, the program capacity may not be required.
In many cases, half that amount (4 plus part-time jobs) is sufficient. Normally, products with built-in ROM are manufactured with a capacity reduced to 4 (items), but products with built-in EFROM,
Since it is mainly used for program development, etc., the amount used is small.

For this reason, it is convenient to be able to use a single product as products with different memory capacities because it increases the degree of freedom, and this is usually done. In this case, if 41 items (pie in 8) are used for part-time use in part 4, there is a problem that part-time part t is not used in the latter part 4.

[Purpose of the invention]

The purpose of the present invention is to solve such conventional problems and to
An object of the present invention is to provide an EFROM-poor microcomputer that can effectively utilize M.

[Structure of the invention]

The configuration of the present invention provides a micro combinator having a built-in EPROM and configured as a semiconductor integrated circuit.
The OM is characterized by comprising means for restricting access to the OM to a plurality of areas of the memory capacity thereof, and means for selecting and allocating the one area to one of the plurality of divisions on the addresses of the memory. .

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of the actual flow side of the present invention. In the figure, 1 is a control circuit, 2 is an EPROM (in this case, 8 is a byte capacity), and 3 is a device that receives an address signal 1n-atz from the control circuit 1 and the output of an OR gate 7 to read one address on the EPROM 2. Address decoder to select.

8 is the content of EPROM2, that is, the instruction code;
Reference numeral 9 indicates various control signals which the control circuit 1 decodes and outputs from the instruction code 8, and the destination of this control signal 9 is not shown. In addition, 12 is a reset terminal, 11 is a switching signal terminal for switching EP OM2 to use 8 bytes or 4 bytes, and 10 is an EFROM when byte use is selected for 4.
This is a terminal for selecting the first half of 2 or the second half of 4 bytes. When selecting byte 4, Nant gate 13 notifies control circuit 1 that the address is greater than or equal to 4, and outputs EPR.
This is to stop the output of OM2. Next, each selected state will be explained.

(1) When all bytes are used for EPR, 0M3 A signal of logic value "0" (hereinafter referred to as positive logic description, logic value rOJ is described as low level and logic value "1" as high level) is input from terminal 11. Then, the Nant gate 13 is at a high level, and the EPROM 2 outputs an instruction code corresponding to the address.

AND gate 6 is at low level regardless of terminal 10.
The AND gate 5 is opened because the inverted signal of the terminal 11, that is, a high level signal is input through the inverter 9 to one input thereof, and the address signal ata from the control circuit 1 is input to the OR gate 7 as it is. Since the output of this art/togatero is at a low level, the output of the OR gate 7 is the address signal ata and is input to the address decoder 3.

When a reset signal is input to the reset terminal 12, the control circuit 1 outputs an address signal ao=ata (aQ is the lower order).

a13 is the most significant bit) from address O to IFFFH
Byte access can be made up to the address, ie, up to 8 addresses.

(2) In the case of byte access to the first half 4, high level signals are input to terminals 11 and 12. When the control circuit 1 attempts to access the EFROM 2 with an address equal to or higher than 4, the address signal a13 becomes high level) and the Nant gate 13 outputs a low level signal. This signal ° is transmitted to the control circuit 1, and the EFROM
2 and stop access to EPR, OM 2.
The instruction code output is also transmitted to stop the instruction code output.

In this way, the number of accesses to EPROM 2 is within four.

Since terminal 11 is at high level, it is different from case (1))
, AND gate 5 is closed and AND gate 6 is opened, and the signal from terminal 10 is inputted to address decoder 3 through AND gate 6 and OR gate 7. In this case, by setting the terminal 10 to a low level, the most significant bit of the address input to the EFROM will not be at a low level, and only addresses from address 0 to oF'FFH (byte 4) will be accessed.

(3) Case of byte access to the second half 4 The process is the same as in case (2) except that the terminal 10fC is set to high level. From now on, a high level will be transmitted to the address decoder 3 through the path described above, that is, the most significant address bit of the EFROM 2 will not be at a high level, and the control circuit 1
Even if accessing address EFFFH from address 0, EPRO
On M2, bytes are accessed from address 100OH to IFPF address 4.

FIG. 2 is a layout diagram showing access areas of the EFROM corresponding to these three states. The shaded area represents the area to be accessed. In FIG. 2, when A is logic "O-" from terminal 11.10 (1), when accessing byte to 8, when B is logic "10" (2), byte is accessed to the first half 4,
When C is logic "11" (3), the second half 4 corresponds to byte access.

In this embodiment, the byte is divided into two parts in the EPROM 8, but by adding circuits and terminals, it is possible to divide the byte into more parts.

〔Effect of the invention〕

As described above, according to the present invention, in a microcomputer configured as a semiconductor integrated circuit with a built-in EPROM, a plurality of programs up to 1/n of the EFROM capacity can be evaluated by the same microcomputer. In addition, as a result of debugging, when rewriting and evaluating a modified program, normally it is necessary to erase the EPROM before writing, but since the latter 4 bytes can be used, there is no need to go through the trouble of erasing. , it is possible to write and evaluate the latter half of 4k, saving the time required for erasing.

Furthermore, different programs can be written into the first half 4 and the second half 4 of the EPROM, respectively, and a plurality of programs can be evaluated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, and FIG. 2 is a layout diagram of the EFROM access area of FIG. In the figure, 1... control circuit, 2... EPROM,
3... Address decoder, 4... Inverter, 5, 6... AND gate, 7...
...OR gate, 8...Instruction code signal, 9.
...Various control signals %aO-a13...Address signal, 10.11...Input terminal, 12.
. . . Reset terminal, 13 . . . Nantes gate. l E-1゛Representative Patent Attorney Susumu Uchihara ('','-1゜゛(
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Claims (1)

[Claims] In a microcomputer configured as a semiconductor integrated circuit and having a built-in read-only memory that can be written, erased, and readable, means for restricting access to the built-in memory to an area that is a plurality of areas of the memory capacity; A microcomputer comprising means for selecting and allocating to one of the plurality of address divisions of the memory.