JPS61161551A - Performance analyzer - Google Patents

Abstract

PURPOSE:To measure accurately a running time by dividing the running state of a target microprocessor (muP) between standard subroutine running parts and user generated program running parts to manage the running state. CONSTITUTION:Address information of the running target muP is stored in a data register 1 in relation to the operation timing of the target muP. A stored address AD is sent to address detecting circuits 2 and 3. When the address is increased, the output of the address detecting circuit 3 goes to the high level, and a counter 5 is stopped. When the address is increased furthermore, the counter 5 starts the counting operation. When the address is increased furthermore, the counting operation of the counter 5 is interrupted. When the execution of a subroutine is terminated and the address is returned to an address in a program area, the counter 5 restarts the counting operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement of a performance analyzer useful in developing software for micro-processor and other application equipment.

(Previous technology) Conventionally, there is a performance analyzer that can measure the program processing time of a microprocessor. This analyzer is used to shorten execution time and improve processing performance in software development for microprocessor and other application devices.

(Problems to be solved by the invention) However, with conventional performance analyzers,
As shown in Figure 3, the measurement was limited to the time taken to pass between two points A and B of the program created. Program designers aim to shorten the execution time between A and 8 and increase processing performance, but if this program calls subroutines of standard utilities that have already been created, The execution time was measured, including the processing time of subroutines C-4D and E→F, and it is difficult to accurately determine the processing time of only the program created by the designer, so which part of the program should be modified to improve performance. The problem was that it was difficult to understand.

In view of these points, it is an object of the present invention to perform processing routines created in advance (for example, C→D and B-4F in FIG. 3).
It is an object of the present invention to provide a performance analyzer that makes it possible to measure the execution time of a portion other than the processing routine (processing routine).

(Means for Solving the Problems) The present invention to achieve such an object includes a detecting means for detecting the start address and the final address in a program whose execution time is to be measured, and a means for detecting the time measurement. and a control means for stopping the counting operation of the counter when an address outside the range of the first address and the last address runs, and a control means that stops the counting operation of the counter when the address runs outside the range of the first address and the last address, The present invention is characterized in that the running time of the program to be executed is not counted, and only the program processing time of the designated section is obtained by the counter.

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram of main parts of a performance analyzer according to the present invention. In the figure, l is a data register that receives information about the target microprocessor (hereinafter referred to as data) (abbreviated as IJP), 2 is a first address detection circuit,
3 is a second address detection circuit.

The first address detection circuit 2 detects whether the address output from the data register 1 is within a preset address range. , Pflo, and P23. The first address comparator 21c is set in advance as the first address person, and generates a set signal to set the flip-flop 23 when the output address (assumed AD) of the data register 1 matches the person. On the other hand, the second address divider 2
The final address B is also set in advance for AD 2, and when AD matches B, a reset signal is sent out to reset the book 23.

The second address detection circuit 3 detects whether the address is within the range of a preset address (0 and H, and the range between G and H includes the range between A and B). The circuit is composed of a first address comparator 31, a second address comparator 32, and a gate 33. The first address comparator is 1 when AD)G.
Sends out a signal at H6 level and selects the second address comparator AD>I(Oto!')! 'Send out a level signal. The gate 32 outputs an AND signal of these two signals, and outputs an output signal of 1H level when AD (H).

A counter 5 receives the output of a gate 4 obtained by gate-processing the outputs of the address detection circuits 2 and 3 as a count enable signal, and counts the basic tally and ri.

Note that clocks for the target IJP and the target IJP are given to the data register 1 and the first address detecting circuit 2, respectively, and storage operations are performed in synchronization with the timing of this clock. It looks like this.

The operation in such a configuration will be explained next.

Let us take as an example the case where the program space of the IF is configured as shown in FIG. Here, the program space P is separated and located to improve performance.

The address information of the running data, )pp is the data y)
Data register IK in relation to IJP operation timing
be remembered. The stored address AD is sent to address detection circuits 2 and 3. As the address increases, A
D) When it becomes G, the output of the second address detection circuit 3 becomes 1.
It appears in H Lebel. - Since the address detection circuit 2 of the address detection circuit 2 with power failure 1 is in the state of AD A, the Q
The output is at ILI level, so the output of gate 4 is also l
The counter 5 is at L'' level and is in a stopped state.

When the address advances and AD=AK, the p-flop 23 is set by the output signal of the address comparator 21 and the Q output is inverted to 1H level.

As a result, the output of the gate 4 becomes lHl level, and the counter 5 starts counting the basic clock CLK. When the address advances and reaches the address of the subroutine area, the output of the second address detection circuit 3 becomes 1 and the output of the rounding gate 4 also becomes level Ill~, and the clock counting operation of the counter 5 is interrupted.

When the execution of the subroutine ends and the address returns to the address of the program area P, the output of the second address detection circuit 3 becomes 1) 1) level again. As a result, the clock counter 5 restarts the clock counting operation. The count value is accumulated to the value before the interruption.

Clock counting is performed in this manner until the address AD reaches B, and when the address exceeds B, the count enable signal is always at the K@L@ level and no clock counting is performed.

As a result, the execution time of the program of the address detection circuit excluding the subroutine program portion can be obtained from the counter 5.

Note that address comparators 21, 22, 31:
The setting value of 32 can be changed as appropriate, and can be set to any desired address.

The second address detection circuit 3 is not limited to the configuration of the embodiment. For example, a normal RAM is used, and address data can be set therein in the format of 1 byte (f'), and each bit is 0.1. X (Don't Care Don't
By employing an address detection circuit that is configured to allow setting of ``care'', it is possible to measure performance not in a unified area but in discrete areas, making it possible to perform more detailed performance measurements.

(Effects of the Invention) As explained above, according to the present invention, data,
Since it is possible to separate and manage the standard subroutine running part and the user-created program running part depending on the running state of P, it is possible to accurately measure the running time and decide which part of the program should be improved. Yongchang will be able to understand if the speed should be improved.

[Brief Description of the Drawings] The flEx diagram is a main part configuration diagram showing one embodiment of the performance analyzer according to the present invention, Figure 2 is an explanatory diagram showing an example of the program space of Targetera uP, and Figure 3 is a diagram of the conventional FIG. 3 is a diagram for explaining how execution time is measured in a performance analyzer. l...'y'-pv register, 2... first address detection circuit, 3... second address detection circuit, 4.33
...Taku, 5 River Counter, 21.22.31.32
...address comparator, 23...7 lipflop 〇ζ target! −

Claims (1)

[Claims] A data register that receives address information from the target microprocessor, and a start address and a final address for measuring the execution time of a program executed by the target microprocessor are set, and it is detected whether the address given from the data register is between these addresses. a first address detection circuit; a second address detection circuit that detects whether a specific address range including the first address and the last address is set and the address given from the data register is within this address range; , a counter that measures time by counting clocks,
comprising means for controlling a time measurement operation of the counter in relation to the outputs of the first address detection circuit and the second address detection circuit, and the target microprocessor is set with the second address detection circuit. A performance analyzer characterized in that when running within an address range and between addresses set by the first address detection circuit, the execution time during that time can be obtained from the counter.