JPS61161549A - Parity check system of microprogram storage memory - Google Patents

Abstract

PURPOSE:To shorten the processing time by generating addresses of a microprogram storage memory successively to read out a microprogram and performing parity check when specific information is sent from a central processing unit of a current system. CONSTITUTION:In case that a central processing unit 2 of a stand-by system is checked, a central processing unit 1 of the current system reads out control information from a main storage device 3 and sets it to a shift register 11. This information is set to a shift register 21 of the central processing unit 2 of the stand-by system. A sequence control part 26 starts the sequence of parity check when a parity check designating flip flop 25 is set. The sequence control part 26 outputs the microaddresses stored in a microprogram storage memory 27, and a parity check circuit 28 performs parity check of the outputted microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for performing a parity check on a memory storing microprograms in a redundant central processing unit, and in particular, the present invention relates to a method for checking the parity of a memory storing microprograms in a redundant central processing unit, and in particular, (
This invention relates to a parity check method used when a SBY) system central processing unit checks all areas of a microprogram memory during diagnosis.

In the redundant central processing unit (CC), the active CG (8CT-CC) is connected to the standby CC (SBY-CC).
Before switching to CC), it is necessary to perform a parity check on all areas of the microprogram of the standby CC in order to confirm the normality of the standby CC.

[Traditional technique]

Conventionally, when performing a parity check of such a microprogram storage memory, the clock supply from the active CC to the standby CC is stopped, and then the address of the microprogram storage memory in the standby CC is changed. The contents of the microprogram are sequentially specified in the standby CC, and the standby CC then performs a parity check. At this time, standby C
The reason why the C stops supplying the clock is to prevent the standby CC from performing operations under the control of the microprogram by reading out the microprogram.

[Problem that the invention seeks to solve]

In the conventional parity check method for microprogram storage memory, it is necessary to send the address of the microprogram of the standby CC for parity check one by one from the active CC to the standby CC. There is a problem in that the processing time required to check the microprogram storage memory becomes significantly long.

[Means for solving problems]

A parity check method for a microprogram storage memory according to the present invention provides a means for transmitting specific information in an active central processing unit, and a means for detecting the specific information in a standby central processing unit. When this specific information is detected, the microprogram generation means sequentially generates the address of the microprogram storage memory, reads the microprogram, and performs a parity check.

[For production]

In the method of the present invention, when specific information is sent from the active central processing unit, the standby central processing unit determines that it has been instructed to perform a parity check, sequentially generates addresses in the microprogram storage memory, and reads the microprogram. Therefore, when performing a parity check of the microprogram storage memory of the standby central processing unit, there is no need to send the microprogram address one by one from the active central processing unit, and the clock of the standby central processing unit is There is also no need to process supply interruptions.

〔Example〕

The figure shows an embodiment of the parity check method for the microprogram storage memory of the present invention, in which 1 indicates the active CG (ACT-CC), and 2 indicates the standby CG.
(SBY-CC), 3 is the main memory of the active system CC, and in the active system CCI, 11 is the shift register (SBY-CC).
FR), 12 is a transfer control unit. Also, standby CC2
21 is a shift register (SFR), 22 is a gate, 1 is an all "O" detection section, U is a gate, 4 is a parity check specification flip-flop, 2 is a sequence control section, 27 is a microprogram storage memory (CM)
, 28 is a parity error check circuit, 29 is an interrupt (I
S) Flip-flop; 30 is a microprogram storage register (CMIR);

When checking the standby CC2, the active CCI
reads control information at the time of check from the main storage device 3 and sets it in the shift register 11. This information includes a command part (CHD) for parity check execution of the microprogram and a specific address of the microprogram (μP) address, for example, all "0". This information is sent, for example, serially to the standby CC2 based on transfer control from the transfer control unit 12 in the active CC, and is set in the shift register 21 in the standby CC2.

At the end of transfer, when the activation signal is sent from the transfer control unit 12 of the active CCI and the signal 5TOP indicating the operation stop state of the standby CC is generated, the command part (CHD) set in the shift register 21 is sent. An output is then generated from the gate 22. On the other hand, the all "0" detection section command is for all microprogram (μP) addresses set in the upper part of the shift register 21.
0'' is detected and an output is generated. Thereby, the gate 24 generates an output and sets the parity check designation flip-flop 5.

The sequence control unit starts a parity check sequence when the flip-flop is set. The sequence control unit side has a microprogram storage memory n.
Outputs a microaddress to control the parity check of the microprogram stored in the microprogram.

The microaddress corresponds to the total number of words in the microprogram, and its initial value is all "0",
+1 will be added sequentially. The microprogram storage memory 27 thereby sequentially outputs all microprograms.

The parity error check circuit 28 sequentially checks the parity of the output microprogram, and sets the interrupt flip-flop 29 when an error is detected. As a result, the active CCI is interrupted, and the active CCI can recognize that the standby CC2 is not normal.

The microprogram storage register 30 normally transfers the microprogram read from the microprogram storage memory 27 into the standby system CO2, and thereby the standby system CC2 performs the required operation, but during parity check execution, the microprogram is transferred to the standby system CO2. Storage register 30 is NOP
(disabled), the microprogram is not output, and therefore the standby system CC2 does not start operating according to the microprogram.

When the micro address of the sequence control unit exceeds the count, that is, when the parity check is completed, an address over signal is output, the parity check designating flip-flop 5 is cleared, and the sequence control unit 26 is thereby initialized. At the same time, the microprogram storage register 30 is released from NOP, and the standby system CC2 becomes operable.

〔Effect of the invention〕

As explained above, according to the microprogram storage memory parity check method of the present invention, the means for transmitting specific information is provided in the active central processing unit, and the means for detecting the specific information is provided in the standby central processing unit. When this specific information is detected in the standby central processing unit, the microprogram generating means sequentially generates the address of the microprogram storage memory, reads the microprogram, and performs a parity check. When the processing unit performs a parity check on the microprogram storage memory in the standby central processing unit, it is no longer necessary to send the microprogram address one by one from the active central processing unit, and the processing time for the parity check is therefore significantly reduced. Ru. Furthermore, there is no need to stop the clock supply to the standby central processing unit, which simplifies the processing.

[Brief explanation of the drawing]

The figure shows an example of a parity check method for a microprogram storage memory.
Standby central control unit (SBY-CC), 3-main memory,
11...Shift register (SFR), 12...
-1 transfer control unit, 21-shift register (SPR),
22.-Gate, all “O” detection section, 24.-Gate, section-Parity check specification flip-flop, 2
6～・-Sequence system? Part 11, 27-Microprogram storage memory (CM), n--Parity error check circuit, 4--Interrupt (Is) flip-flop, 30
-Microprogram storage register (CMIR)

Claims (1)

[Claims] In a method in which an active central processing unit performs a parity check of a microprogram storage memory in a standby central processing unit, means for transmitting specific information is provided in the active central processing unit, and means for detecting the specific information is provided on standby. The system is provided in the system central processing unit, and when the specific information is detected in the standby system central processing unit, the microprogram generating means sequentially generates the address of the microprogram storage memory, reads the microprogram, and performs a parity check. A parity check method for microprogram storage memory.