JPS61159845A - Loop type lan hybrid multiplexing system - Google Patents

Abstract

PURPOSE:To cope with its large capacity easily at a high speed by a combination of an asynchronous system packet switching circuit and a synchronizing system line switching circuit by constituting a titled system so that a packet switching circuit part of plural nodes uses a synchronizing bit position of a PCM frame as a time by taking synchronization to a time division multiplex transmission line interface. CONSTITUTION:Each node 30 is constituted of a loop access controlling circuit 31, a circuit switching device part 32, and a packet switching device part 33. This multiplexing system has an asynchronous oscillator to a transmission line 1, and also can take a timing buffer of a one bit portion of a synchronizing bit position at every one frame (193 bits), therefore, an oscillator of low accuracy can be used. A circuit 33A is constituted of the same interface as the circuit switching device, knows the synchronizing bit position by receiving a frame synchronizing signal from the controlling circuit 31, eliminates (n) pieces of data of that position, and brings data of (n)X192 bits to multiplex separation. In this way, it is unnecessary to provide an oscillator synchronized with a loop transmission line, an elastic buffer delay time of the data is small, and it can be transferred continuously so as to be asynchronous to all bits.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a loop local area network (LA
In particular, the present invention relates to a multiplexing method in a hybrid time division multiplex transmission line that transmits circuit-switched data and packet-switched data.

Conventional technology Conventional loop-type LANs were mainly high-speed circuit-switched loop-type LANs using time division multiplexing technology and asynchronous packet transfer loop-type LANs, but recent advances in light wave technology have increased speeds from 100 Mbps to several hundred Mbps. A loop-type transmission line using optical fiber with a transmission speed of It is multiplexed by assigning it as . Therefore, according to the frame configuration and channel allocation method in high-speed time division multiplex transmission and the intra-loop transfer packet data frame configuration method, the hardware of the loop access control section of each node station is made of high-speed logic circuit elements and system-specific hardware. It is necessary to adopt the following logic circuit configuration.

Problems to be Solved by the Invention However, it is not economical to speed up extensive circuitry at each node station. In addition, the packet-switched data accommodated in this time-division multiplexing transmission line is originally asynchronous and can be processed independently of the synchronous frames of the synchronous time-division multiplexing transmission line, but packet switching is required for hybrid multiplexing. The system loop access control section also needed to be constructed from high-speed logic circuits synchronized with the transmission path.

FIG. 4 is a configuration diagram of a conventional loop type LAN.

In the figure, each node station 3 connected by a high-speed time division multiplex loop transmission line 1 has a circuit switching function and a packet switching function, and a central station 2 has a loop synchronization circuit, a system failure monitoring function, etc. .

The present invention has been made to solve the above-mentioned rc+1 problem inherent in the conventional technology, and therefore, the purpose of the present invention is to:
The packet switching circuits of multiple node stations connected to a high-speed, large-capacity loop transmission line use the synchronization bit position of the PCM frame as the synchronization time with the time division multiplex transmission line interface, thereby converting conventional asynchronous packets. The object of the present invention is to provide a new hybrid multiplexing system that can easily handle high speed and large capacity by combining a switching circuit and a synchronous line switching circuit.

Means for Solving the Problems In order to achieve the above object, the I-brid multiplex system according to the present invention is a time division multiplex digital system in which a plurality of node stations each having a circuit switching function and a packet switching function are arranged in a loop. In a loop-type LAN connected to a transmission line,
A method is adopted in which n PCM frames of several multiplexed high-speed time division multiplexed transmission lines are exclusively allocated as an asynchronous packet-switched data transmission line, and at this time, the synchronization within the PCM frame is The time of one bit position is multiplexed into n PCM frames and the packet serial data of the packet switching circuit interface.

The present invention is characterized in that it is used as synchronization buffer timing for separation to realize the asynchronous packet exchange function.

Embodiments of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 shows one embodiment of the present invention, and is a block diagram of a hybrid loop type LAN in which each node station 3 in FIG. 4 is shown with a configuration according to the present invention. Each node station consists of a loop access control circuit 311, a line switching device section, and a packet switching device section.
A high-speed time division multiplex transmission line on which CM frames are multiplexed is separated into M frames by the loop access control circuit 31, and M-n frames are connected to the line switching device section n. Using conventional time-division circuit switching technology, the circuit switching function can be easily included in this loop fi LAN, and it can be preempted without being influenced by the packet switching system configuration.In addition, n PCM 7 frames can be The packet switching device is exclusively connected to the packet switching device.Here, the packet switching device (as shown in FIG. By replacing 33B with the circuit 33A shown in FIG. 3, which uses the multiplexing method of the present invention, it can be handled with a conventional hardware module.Here, for the U channel PCM frame, As shown in Figure 2, in the 193-bit frame format that makes up one frame, there is one bit that is not used for data transfer as a synchronization bit.However, the non-standard method uses the time of this synchronization bit position. This method processes n pieces of 192-bit data each in one frame of 193-bit time, and connects it to the high-speed packet serial data interface of a conventional packet switching device.

This multiplexing system shown in FIG. 3 has an oscillator that is asynchronous with the loop transmission line 1, and as shown in FIG.
Since a timing buffer for one synchronous bit position can be provided for every 193 pits), a low-precision oscillator can be used.

The circuit 33A has the same interface configuration as the line switching device, receives a 7V-me synchronization signal from the loop access control circuit 31, learns the synchronization bit position, and, excluding n data at the synchronization bit position, stores n x 192 bits of data. This is a circuit that demultiplexes.

With this method, there is no need to have an oscillator synchronized with the loop transmission line, and data elastake buffers (Elastake buffers) can be used.
tic Buffer) Because the delay time is small and the system exclusively uses n PCM frames, all bits except the synchronization bit are Since continuous transfer can be performed asynchronously, the effective transfer speed is also improved.

Effects of the Invention As explained above, the present invention exclusively uses n PCM 7 frames as an asynchronous packet-switched data transfer path.
In addition, by adopting a method in which the synchronization bit on the PCM frame is used as a timing buffer for synchronization with the input multiplexing interface section (loop access control circuit), lines connected through high-speed time division multiplexing transmission lines, Each node station, which has switching and packet switching functions, requires only a minimum high-speed logic circuit such as a loop access control circuit, and it can be configured using circuit switching equipment and packet switching equipment modules that have a hardware configuration based on conventional scale and methods. Since it can be handled in a distributed configuration, it is possible to realize a LAN with ease and flexibility in system design. Also,
This also has the effect of improving the effective transfer of packet systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a loop-type LAN having a no-brid exchange function according to the present invention;
The figure is a frame format diagram of a channel PCM frame, FIG. 3 is a functional block diagram showing the details of the packet switching device interface section that constitutes the multiplexing method of the present invention, and FIG. 4 is a diagram of a conventional loop type LAN. Configuration diagram 1. @5
This figure is a block diagram of a packet-switched loop type LAN constructed of the packet-switched device modules shown in FIG. 1. 1.10... High-speed time division multiplexed loop transmission line, 2...
Central node station, 3.30...Remote node station, 31...Loop access control circuit, 32...Line switching device section,...Packet father switching device section, 33A, 33B...Loop access Control circuit interface section patent applicant NEC Corporation Representative Patent attorney Yuta Kumagai Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] In a loop LAN in which multiple node stations equipped with circuit switching and packet switching functions are connected to a loop-shaped time-division multiplexing digital transmission line in which multiple 24-channel PCM frames are multiplexed, n PCM frames are transmitted. At this time, the time of one synchronous bit that is not used for data transfer within the PCM frame is n.
A loop type LAN hybrid multiplexing system characterized in that the packet switching function is realized by using a real PCM frame and a packet switching circuit interface as a synchronization buffer timing for multiplexing and demultiplexing packet serial data.