JPS61156885A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS61156885A
JPS61156885A JP59276363A JP27636384A JPS61156885A JP S61156885 A JPS61156885 A JP S61156885A JP 59276363 A JP59276363 A JP 59276363A JP 27636384 A JP27636384 A JP 27636384A JP S61156885 A JPS61156885 A JP S61156885A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
polycrystalline
semiconductor device
silicon layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59276363A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0466108B2 (enrdf_load_stackoverflow
Inventor
Yoshimi Shiotani
塩谷　善美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59276363A priority Critical patent/JPS61156885A/ja
Publication of JPS61156885A publication Critical patent/JPS61156885A/ja
Publication of JPH0466108B2 publication Critical patent/JPH0466108B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP59276363A 1984-12-28 1984-12-28 半導体装置の製造方法 Granted JPS61156885A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59276363A JPS61156885A (ja) 1984-12-28 1984-12-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276363A JPS61156885A (ja) 1984-12-28 1984-12-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS61156885A true JPS61156885A (ja) 1986-07-16
JPH0466108B2 JPH0466108B2 (enrdf_load_stackoverflow) 1992-10-22

Family

ID=17568381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59276363A Granted JPS61156885A (ja) 1984-12-28 1984-12-28 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS61156885A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029136A (ja) * 1988-03-22 1990-01-12 Internatl Business Mach Corp <Ibm> 薄膜電界効果トランジスタの製造方法
JPH0284768A (ja) * 1988-09-21 1990-03-26 Nec Corp 固体撮像素子の製造方法
US5561075A (en) * 1991-05-08 1996-10-01 Seiko Epson Corporation Method of manufacturing an active matrix panel

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH029136A (ja) * 1988-03-22 1990-01-12 Internatl Business Mach Corp <Ibm> 薄膜電界効果トランジスタの製造方法
JPH0284768A (ja) * 1988-09-21 1990-03-26 Nec Corp 固体撮像素子の製造方法
US5561075A (en) * 1991-05-08 1996-10-01 Seiko Epson Corporation Method of manufacturing an active matrix panel
US5583366A (en) * 1991-05-08 1996-12-10 Seiko Epson Corporation Active matrix panel
US5814539A (en) * 1991-05-08 1998-09-29 Seiko Epson Corporation Method of manufacturing an active matrix panel
US6136625A (en) * 1991-05-08 2000-10-24 Seiko Epson Corporation Method of manufacturing an active matrix panel

Also Published As

Publication number Publication date
JPH0466108B2 (enrdf_load_stackoverflow) 1992-10-22

Similar Documents

Publication Publication Date Title
US4621276A (en) Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4505027A (en) Method of making MOS device using metal silicides or polysilicon for gates and impurity source for active regions
US4510670A (en) Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors
EP0225920B1 (en) Process for forming contacts and interconnects for integrated circuits
US4677735A (en) Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US7622740B2 (en) Semiconductor device and method of fabricating the same
US4453306A (en) Fabrication of FETs
EP0249780B1 (en) Semiconductor device with a wiring layer having a good step coverage at contact holes
US4822749A (en) Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
KR960001602B1 (ko) 집적회로 제조방법
US5173450A (en) Titanium silicide local interconnect process
JP3067847B2 (ja) Ｍｉｓ集積回路の活性層上に電気的接触を形成する方法
JPS6173370A (ja) 半導体装置及びその製造方法
US4364166A (en) Semiconductor integrated circuit interconnections
US4822754A (en) Fabrication of FETs with source and drain contacts aligned with the gate electrode
EP0173734A1 (en) Improved integrated circuit structure having intermediate metal silicide layer and method of making same
US4737831A (en) Semiconductor device with self-aligned gate structure and manufacturing process thereof
US5373178A (en) MOSFET with sidewall spacer on gate section
US4937657A (en) Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
US5840618A (en) Method of manufacturing semiconductor device using an amorphous material
US6100186A (en) Method of selectively forming a contact in a contact hole
KR100433509B1 (ko) 전계 효과 트랜지스터, 집적 회로, 전계 효과 트랜지스터 형성 방법, 그리고 집적 회로 형성 방법
JPS61156885A (ja) 半導体装置の製造方法
US7329599B1 (en) Method for fabricating a semiconductor device
KR940004450B1 (ko) 반도체장치의 제조방법

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees