JPS61155929U - - Google Patents
Info
- Publication number
- JPS61155929U JPS61155929U JP4063885U JP4063885U JPS61155929U JP S61155929 U JPS61155929 U JP S61155929U JP 4063885 U JP4063885 U JP 4063885U JP 4063885 U JP4063885 U JP 4063885U JP S61155929 U JPS61155929 U JP S61155929U
- Authority
- JP
- Japan
- Prior art keywords
- main power
- microcomputer
- voltage
- cut
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
及び第３図は第１図に示された実施例の動作を示
す各部電圧波形図である。
主な図番の説明、１……電圧保持回路、２……
マイクロコンピユータ、６……遮断検出回路、１
１……リセツト信号発生回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are voltage waveform diagrams of various parts showing the operation of the embodiment shown in FIG. Explanation of main drawing numbers, 1... Voltage holding circuit, 2...
Microcomputer, 6... Cutoff detection circuit, 1
1...Reset signal generation circuit.
Claims (1)
出したときホールト命令の実行により動作を停止
し、リセツト端子に印加されるリセツト信号によ
り動作を開始するマイクロコンピユータに於いて
、主電源が遮断されたときバツクアツプ電圧を前
記マイクロコンピユータに供給する電圧保持回路
と、前記主電源と接地間に接続され前記主電源の
遮断を遅延して前記入力端子に印加する時定数ｔ
１の放電回路を有する遮断検出回路と、前記主電
源の復帰及び遮断によつてオン及びオフされるト
ランジスタと前記電圧保持回路の電圧出力との間
に設けられた抵抗及びコンデンサから成る充電回
路及び前記コンデンサに並列接続され時定数ｔ２
の放電回路を有するリセツト信号発生回路とを備
え、前記時定数ｔ１及びｔ２はｔ１＞ｔ２である
ことを特徴とするマイクロコンピユータのスタン
バイ制御回路。 In microcomputers that stop operation by executing a halt command when a standby request signal applied to an input terminal is detected, and start operation by a reset signal applied to a reset terminal, backup is performed when the main power supply is cut off. a voltage holding circuit that supplies voltage to the microcomputer; and a time constant t that is connected between the main power source and ground and delays the shutoff of the main power source and applies it to the input terminal.
1 ; a charging circuit comprising a resistor and a capacitor provided between a transistor that is turned on and off when the main power supply is restored and cut off; and a voltage output of the voltage holding circuit; connected in parallel to the capacitor and has a time constant t 2
1. A standby control circuit for a microcomputer, characterized in that the time constants t 1 and t 2 are such that t 1 >t 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4063885U JPH0342496Y2 (en) | 1985-03-20 | 1985-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4063885U JPH0342496Y2 (en) | 1985-03-20 | 1985-03-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61155929U true JPS61155929U (en) | 1986-09-27 |
| JPH0342496Y2 JPH0342496Y2 (en) | 1991-09-05 |
Family
ID=30549713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4063885U Expired JPH0342496Y2 (en) | 1985-03-20 | 1985-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342496Y2 (en) |
-
1985
- 1985-03-20 JP JP4063885U patent/JPH0342496Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0342496Y2 (en) | 1991-09-05 |
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