JPS61154049A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the formation of a contact window having a high dielectric strength by a method wherein an indent around a first conductor pattern having an oxidation-resisting mask film is filled up with an etching mask layer and an exposed portion of the oxidation-resisting mask is removed selectively with said etching mask layer as a mask. CONSTITUTION:A substrate is spin-coated with an etching mask layer, e.g. a resist film 23, being thick enough to fill up an indent located between gates. Next, the resist film 23 is removed by etching from the top so that an Si3N4 film 22 is exposed, and indents 24a, 24b, 234c, 24d and 234e located between gate electrodes are filled up selectively with the resist film 23. Next, the resist film 23 in the indents being used as a mask, the Si3N4 film 22 exposed on gate electrodes 4a, 4b, 4c and 4d and ion the top of an SiO2 lower-layer insulating film 7 located on the side of said gate electrodes is removed selectively by dry etching, and thereby a polycrystalline silicon layer 21 in a region is exposed selectively. Then, thermal oxidation is applied with the Si3N film 22 used as a mask, and thereby an SiO2 film 25 is formed selectively on the exposed surface of the polycrystalline silicon layer 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, in which a self-alignment line is formed in the vicinity of a first conductor pattern. The present invention relates to an improvement in the method of forming a contact window of a conductor pattern in No. 2.

Dynamic random access memory (D-RA)
In MOS memories such as M), large scale and high integration are important issues, and in order to achieve this, there is a strong demand for a manufacturing method that can further reduce the cell area.

[Conventional technology]

Figure 5 shows the original one-transistor, one-capacitor structure D-
FIG. 2 is a schematic side sectional view showing a RAM cell (two cells).

In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, and 4a, 4b.

4c and 4d are gate electrodes (word lines) made of the first polycrystalline silicon layer PA, and 5 is an n+ type drain region 6a.
, 6b is an n0 type source region, 7 is a lower insulating film, 8 is a contact window, 9a and 9b are second polycrystalline silicon layers PB
10 is a drain electrode made of a second polycrystalline silicon layer PB, 11 is a dielectric film (capacitor film), and 12 is a second capacitor electrode made of a third polycrystalline silicon layer PC. 13 is the upper layer insulating film, 14 is the drain wiring (bit wiring), CI, CI
indicates the first and second cells.

In this initial structure, as is clear from the figure, the drain region 5, the drain electrode 10, the source region 5a,
13b and the first capacitor electrode 9a.

A contact window 8 with 9b was formed in the lower insulating film 7 by mask alignment.

Therefore, it is necessary to form the source and drain regions 5.5a and 6b wide while considering a dimensional margin to absorb mask alignment errors, making it difficult to improve the degree of integration.

Therefore, the source and drain contact windows are connected to the gate electrodes (
Conventionally, a structure has been provided in which a self-line is formed on a word line (word line), thereby reducing the cell area and achieving high integration.

FIG. 6 is a schematic side sectional view showing one transistor/one capacitor memory cell having such a self-line structure of contact windows, and each reference numeral in the figure indicates the same object as in FIG. 5.

Conventionally, the contact window self-aligned to the gate electrode in the above structure has been formed by a method shown in process cross-sectional views of FIGS. 7(a) to (Q).

That is, first, as shown in FIG. 7(a), a field oxide film 2 is selectively formed on, for example, a p-type silicon substrate l by a conventional selective oxidation method, and the field oxide film 2 is defined and exposed. After forming a gate oxide film 3 on the substrate surface by thermal oxidation as usual, chemical vapor deposition (CVD) is performed on the substrate.
D) forming a first polycrystalline silicon layer PA by method,
Then, by the same <CVD method, the polycrystalline silicon layer PA
A first silicon dioxide (Sing) lower layer insulating film 7a having a thickness of, for example, about 2,000 to 3,000 layers is formed thereon.

Next, patterning is performed using a conventional photolithography technique to form gate electrodes (word lines) 4a, 4b, 4c made of PA and having a first Sing lower layer insulating film 7a thereon, as shown in FIG.

4d, and then impurity ions are implanted as usual using the gate electrode as a mask to form an n4 type drain region 5.
and n9 type source regions 6a and 6b are formed.

Next, as shown in FIG. 7(C), a second layer with a thickness of about 2,000 to 3,000 layers is formed on the substrate by CVD.
A tow lower layer insulating film 7b is formed.

Then, the second SiO□ lower insulating film 7b is etched from the upper surface by dry etching, such as reactive ion etching using carbon tetrafluoride (CF) gas, in a direction perpendicular to the substrate surface. source area 5
By uniformly etching the gate electrodes 4a and 5b until the surfaces 5a and 5b are exposed, the gate electrodes 4a and 5b are etched as shown in FIG. 7(d).
4b, 4c, 4d, etc. on the side surfaces of these gate electrodes.
ing self-aligned drain through the lower insulating film 7b.

This was a method of forming contact windows 8 in source regions 5.6a, 6b. (In FIG. 6, the first Sing lower insulating film 7a and the second SiO□ lower insulating film 7b are integrated to form the Sing lower insulating film 7.) [Problems to be solved by the invention] However, the above-mentioned problem In the conventional method, when active ion etching is performed to form the contact window 8, the upper edge UE of the contact window 8, that is, the gate electrodes 4a, 4b, 4c, 4
Since the second SiO2 lower insulating film 7b at the shoulder portions such as d tends to be etched excessively and the corners are shaved off, the etching rate distribution within the substrate surface and the substrate of the second SiO2 lower insulating film 7b may be affected. When the thickness variation in the plane is large, the shoulder portions of the gate electrodes 4a, 4b, 4c, 4d, etc. are exposed, and the gate electrodes are placed on the contact window 8 by the seventh layer.
A capacitor electrode 9a formed as shown in FIG.

This sometimes causes a problem of contact with conductive layers such as the conductive layer 9b and the drain electrode lO.

[Means for solving problems]

The solution to the above problem is to provide a second conductive pattern adjacent to the first conductive pattern placed on the semiconductor substrate via the first insulating film and in contact with the surface of the semiconductor substrate. forming a second insulating film on the semiconductor substrate on which the first conductor pattern is mounted; forming a polycrystalline silicon film on the second insulating film; a step of forming an oxidation-resistant mask film, a step of filling the recesses around the first conductor pattern having the oxidation-resistant mask film with an etching mask layer, and a step of forming the oxidation-resistant mask film using the etching mask layer as a mask. A step of selectively removing the exposed portion, a step of removing the etching mask layer, and using the remaining oxidation-resistant mask film as a mask, the polycrystalline silicon film on the first conductor pattern is partially removed from the silicon oxide layer. a step of selectively removing the oxidation-resistant mask film and the polycrystalline silicon film on the recessed portions using the silicon oxide film as a mask; a step of masking the remaining polycrystalline silicon film on the first conductor pattern; Then, the second insulating film and the first insulating film in the recess are etched by an etching method that is predominant in the direction perpendicular to the substrate surface.
A method for manufacturing a semiconductor device according to the present invention, comprising the steps of selectively removing an insulating film to expose a semiconductor substrate surface within the recess, and forming a second conductor pattern in contact with the exposed semiconductor substrate surface. achieved by.

[Effect]

That is, in the method of the present invention, a different type of film having etching selectivity with respect to the insulating film is selectively formed on the gate electrode and the insulating film on the side surfaces thereof, and a self-aligned contact is made with the gate electrode having the insulating film on the side faces. Rather than forming a window or etching the entire surface using active ion etching, selective etching is performed using the above-mentioned foreign film as a mask. The upper edge of the insulating film on the side surface of the electrode is completely protected by the above-mentioned foreign film, and the upper edge of the insulating film on the side surface of the gate electrode is not scraped off. Seat failure between the drain electrode and the gate electrode is completely prevented.

〔Example〕

Hereinafter, the present invention will be specifically explained by examples with reference to the drawings.

FIGS. 1(a) to 1(1) are process cross-sectional views showing an example of forming one transistor/one capacitor type memory cell;
Figure 2 shows one transistor formed according to the above embodiment.
Schematic plan view of capacitor type memory cell, Figure 3 is ROM
Schematic plan views of the cell, FIGS. 4(a) to (i) are the above RO
FIG. 3 is a process cross-sectional view showing an example of forming an M cell.

The same objects are indicated by the same reference numerals throughout the figures, and the same objects in FIG. 7 are also indicated by the same reference numerals.

Refer to FIG. 1(a) When forming a transistor/capacitor type memory cell by the method of the present invention, for example, a field oxide film 2 is selectively formed on a p-type silicon substrate 1 by a conventional method. , a gate oxide film 3 is formed on the cell formation region defined and exposed by the field oxide film 2, and a first polycrystalline silicon layer PA is formed and extends from the gate oxide film 3 onto the field oxide film 2. After forming the existing gate electrodes (word lines) 4a, 4b, 4c, and 4d, an n9 type drain region 5 and n'-type source regions 13a and 5b are formed using the gate electrodes as a mask.

Referring to FIG.
A SIOM lower layer insulating film 7 with a thickness of about 1,000 mm is formed, and then a film with a thickness of 1,000 to 20 mm is formed using the same CVD method.
A polycrystalline silicon layer 21 with a thickness of about 500 to 1000 nm is formed thereon, and then an oxidation-resistant mask film of about 500 to 1000 layers, such as silicon nitride (Si, N4), is formed on it by the same CVD method.
A film 22 is formed, and then an etching mask layer, such as a resist film 23, is formed on the substrate to a thickness that fills the recesses between the gates.
Spin code.

Referring to FIG. 1(C), the resist film 23 is etched away by oxygen (Ol) plasma treatment or the like until the Si3N film 22 is exposed from the upper surface, and the recesses 24a+ between the gate electrodes (words M) are removed.
24b* 24c+ 24cL 24e is selectively filled with a resist film 23.

Referring to FIG. 1(d), the gate electrodes 4 as 4 b, 4 c, 4 d and the upper part of the Sing lower layer insulating film 7 on their side surfaces are etched by dry etching using, for example, CFn+Og gas, using the resist film 23 in the recessed portion as a mask. The exposed 5j3N4 film 22 is selectively removed, and the polycrystalline silicon layer 21 in the region is selectively exposed.

See FIG. 1(e) then Si! Using the Na film 22 as a mask, thermal oxidation is performed to selectively form a Sing film 25 with a thickness of about 500 to 1000 on the exposed surface of the exposed polycrystalline silicon layer 21.

At this time, the thickness of the remaining polycrystalline silicon layer in this region is 170 mm.
Approximately 0 to 500 people.

Refer to FIG. 1(f). Next, using the SiO□ film 25 as a mask, the recesses 24a, 24b, 24c, 24d,
Si3N in 24e.

After removing the film 22, the polycrystals are exposed in the recesses by reactive ion etching using a gas such as carbon tetrachloride (CCI), which has anisotropy perpendicular to the substrate surface. The silicon layer 21 is selectively removed to selectively expose the Sing layer insulating film 7 within the recess.

At this time, the polycrystalline silicon layer 21 remains on the gate electrodes 4a, 4b, 4c, and 4d, the Sin on their side surfaces, and the upper part of the lower insulating film 7.

Fig. 1 (Refer to the moromi.)
4 +l(, Sin exposed on the substrate surface by reactive ion etching using gas.

The etching process removes the Sing film 25 on top of the gate electrodes 4a, 4b, 4c, 4d and the SiO2 insulating film 7 on their side surfaces, and removes the polycrystalline silicon layer 21 present in the area. Concave portions 24a, 24b+ 24c, 24d+ 2 between gate electrodes as masks
The Sing lower insulating film 7 and gate oxide film 3 on the bottom surface of the recess are selectively removed, and a contact window 8 is formed that exposes the drain region 5 and source ffl@6a, 61) on the bottom surface of the recess.

Note that since the polycrystalline silicon layer 21 remains on the gate electrodes 4a, 4b, 4c, 4d and the 5ift lower insulating film 7 on their side surfaces as described above, the upper edge of the contact window 8, that is, the upper edge of the contact window 8 during etching, The Sin and lower insulating film 7 on the shoulder portion of the gate electrode are not scraped off.

Refer to FIG. 1(h). Next, a second polycrystalline silicon layer PB having a thickness of approximately 4,000 to 5,000 layers is formed on the substrate, and the polycrystalline silicon layer PB is bonded with the polycrystalline silicon layer PB using a conventional photolithography technique. The polycrystalline silicon layer 21 remaining under the polycrystalline silicon layer 21 is patterned, and the source regions 5a and 5b are formed of the second polycrystalline silicon layer PB in the contact window 8 portion.
First capacitor electrodes 9a and 9b in contact with the drain region 5, respectively, and a drain electrode 10 in contact with the drain region 5 are formed.

Referring to FIG. 1 (1), a dielectric film (capacitor film) 11 is formed on the capacitor electrode by the conventional thermal oxidation method, and a third layer of polycrystalline silicon of about 4000 to 5000 layers is formed on the substrate by the CVD method. A second capacitor electrode 12 made of a layer PC is formed, and an opening 2 for exposing the drain electrode 10 is formed in the second capacitor electrode 12 by a normal photolithography technique.
6 and then phosphosilicate glass (P S
G) A contact window 2 in which a glabellar insulating film 13 is formed, and the drain electrode 10 is exposed on the glabellar insulating film 13.
7 is formed, and the contact window 2 is formed on the glabella insulating film 13.
At step 7, a bit wiring 14 made of aluminum or the like is formed in contact with the drain electrode 10.

Thereafter, although not shown, a cover insulating film is formed, and a memory cell having a one-transistor/one-capacitor structure is completed.

FIG. 2 is a schematic plan view showing a memory cell (an area for two cells) having a one-transistor/one-capacitor structure in the above embodiment. Note that each object is indicated by the same reference numeral as in FIG.

According to the above embodiment, the D-R has a one-transistor/one-capacitor structure in which the drain contact window and the capacitor contact window are formed on the gate electrode by a self-line.
When forming an AM cell, the upper edge of the lower insulating film formed on the surface of the gate electrode, that is, the shoulder portion of the gate electrode, is not damaged.

Therefore, a decrease in breakdown voltage or a seat between the drain electrode or capacitor electrode formed to overlap the gate electrode and the gate electrode can be prevented.

Note that the method of the present invention is not limited to the above-mentioned embodiments, and can also be applied when forming a drain contact (bit line contact window) to a gate electrode (word line) in a ROM cell as shown in the schematic plan view of FIG. also applies. In the figure, 2 is a field oxide film, 4a and 4b are gate electrodes (word lines), 5 is a drain region, 6a and 6b are source regions, 108 is a drain contact window (bit line contact window), and 14 is a bit wiring. shows.

The embodiment will be described below with reference to process cross-sectional views shown in FIG. 4 (al to al).

Refer to FIG. 4(a). A gate electrode 4a is formed by forming a gate oxide film 3 on a p-type silicon substrate l by a conventional method.

4b and n using the gate electrode as a mask.

A type drain region 5 and n+ type source regions 6a and 6b are formed, and then a 2000 to 300%
A SiO lower insulating film 7 with a thickness of about 0.000 nm is formed, a polycrystalline silicon layer 21 with a thickness of about 1000 to 2000 nm is formed on it, and a 5 is Nm film with a thickness of about 500 to 1000 nm is formed on it. A positive resist film 123 is formed on the substrate to a thickness that fills the recesses 24 between the gate electrodes, and exposure is performed using a photomask 8.

L indicates light for exposure.

Refer to FIG. 4) Next, development is performed to remove the area other than the upper part of the recess 24.
The resist film 123 is selectively removed.

Refer to FIG. 4(C) Next, the photoresist film 123 remaining on the upper part of the recess 24 is etched using a developer or the like, and the part other than that filled in the recess 24 between the gate electrodes is selectively removed. do.

Referring to FIG. 4(d), the Si3Nm film 22 exposed outside the recesses 24 is selectively removed by dry etching using the resist film 123 as a mask.

Refer to FIG. 4(e) Next, after removing the resist film 123, thermal oxidation is performed to form a layer of 500 to 1,000 in thickness on the surface of the exposed polycrystalline silicon layer 21.
The Sing membrane has a size of 25 membranes and 5 membranes, about the size of a person. At this time, the surface of the polycrystalline silicon layer within the recess 24 is not oxidized because it is covered with the 5isNn film 22.

Referring to FIG. 4(f), the 5t3N inside the recess 24 is then heated by a method such as phosphoric acid boiling.
4 film 22 is removed and the polycrystalline silicon layer 21 in the recess 24 is removed.
to express it.

Refer to FIG. 4(g). Next, using the SiO□ film 25 as a mask, the polycrystalline silicon layer 21 inside the recess 24 is selectively removed by reactive ion etching using CCl4 gas, and the SiOx lower layer insulating film inside the recess 24 is etched. Show 7.

Figure 4 (see below) For example, CF having anisotropy perpendicular to the substrate surface
The SiOg film exposed on the substrate surface is etched by reactive ion etching using a+Hz gas. Through this etching, the Sing film 2 on the top of the gate electrodes 4a, 4b and the SiO2 lower insulating film 7 on the side thereof is etched.
Using the polycrystalline silicon layer 21, which is formed in a five-film shape 5 and exists in the region, as a mask, the SiO
The lower insulating film 7 is selectively removed, and a contact window 108 exposing the drain region 5 is formed at the bottom of the recess.

Note that the gate electrodes 4a and 4b and their side surfaces are made of sin.

Since the polycrystalline silicon layer 21 remains on the upper part of the insulating film 7, the SiOx lower insulating film 7 on the upper edge of the contact window 108, that is, on the shoulder on the concave side of the gate electrode, is not scraped off during this etching. .

Referring to FIG. 4(1), a wiring material layer is then formed on the substrate by a conventional method, and a polycrystalline silicon layer 21 is formed by a conventional lamination lithography technique.
is removed, and an interlayer insulating film 13 made of PSG or the like is formed on the substrate.
The contact window 108 is formed in the glabella insulating film 13.
A large contact window 27 is formed to expose the contact window 27 and its peripheral portion, and then a bit wiring 14 connected to the drain region 5 via the contact windows 27 and 108 is formed on the interlayer insulating film 13 by a conventional method. .

In this embodiment as well, in the etching for forming the contact window shown in FIG. Since the contact window 108 is not scraped off, the gate electrode 4a,
There is no problem such as breakdown voltage deterioration or short circuit between the bit line 14 formed to overlap with the bit line 4b and the gate electrodes 4a and 4b.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to form a contact window having a high dielectric strength with respect to the word line with a self-line, and this enables highly integrated D-RA.
The reliability and manufacturing yield of semiconductor memory devices such as M-'PROM can be improved.

[Brief explanation of drawings]

FIG. 1 (al to (1)) is a process cross-sectional view showing an example of forming one transistor and one capacitor type memory cell, and FIG. 2 is a one transistor and one transistor formed by the above embodiment.
Schematic plan view of capacitor type memory cell, Figure 3 is ROM
A schematic plan view of the cell, FIGS. 4(a) to (1) are process cross-sectional views showing an example of forming the above ROM cell, and FIG.
-A schematic side cross-sectional view showing a RAM cell; FIG.
A schematic side sectional view showing a single capacitor type memory cell, and FIGS. 7(a) to 7(e) are ψ step sectional views showing a conventional manufacturing method. In the figure, 4a, 4b, 4c, 4d are gate electrodes (word lines), 5 is a drain region, 5a, 5b are source regions, 7 is a silicon dioxide insulating film, 8 is a contact window, 9a, 9b are first capacitors Electrodes: 10 is a drain electrode, 21 is a polycrystalline silicon layer, 22 is a silicon nitride film, 23 is a resist film, 24a, 24b, 24C, 24d, 24e are recesses between gate electrodes, and 25 is a silicon dioxide film. $r I! 1 To t Utaban 2 Drunken 3 Utaken 4 Machine 4I! r ￥-S Utaken wo Drunken Body 7 Drunkenness

Claims (1)

[Claims] A second conductor pattern adjacent to the first conductor pattern placed on the semiconductor substrate via the first insulating film and in contact with the semiconductor substrate surface.
When providing a conductor pattern, forming a second insulating film on the semiconductor substrate on which the first conductor pattern is mounted, forming a polycrystalline silicon film on the second insulating film. a step of forming an oxidation-resistant mask film on the polycrystalline silicon film; a step of filling the recess around the first conductor pattern having the oxidation-resistant mask film with an etching mask layer; A step of selectively removing the exposed portion of the oxidation-resistant mask film using a mask, a step of removing the etching mask layer, and a step of removing the exposed portion of the oxidation-resistant mask film using the remaining oxidation-resistant mask film as a mask. a step of converting the polycrystalline silicon film into a silicon oxide film halfway; a step of selectively removing the oxidation-resistant mask film and the polycrystalline silicon film on the recessed portions using the silicon oxide film as a mask; and the first conductor pattern. The second insulating film and the first insulating film in the recess are selectively removed by etching that is predominant in the direction perpendicular to the substrate surface using the remaining polycrystalline silicon film as a mask, and the semiconductor substrate in the recess is removed. A method for manufacturing a semiconductor device, comprising the steps of exposing a surface, and forming a second conductor pattern in contact with the exposed semiconductor substrate surface.