JPS61152190A - Digital chrominance signal processing circuit - Google Patents

Digital chrominance signal processing circuit

Info

Publication number
JPS61152190A
JPS61152190A JP28170484A JP28170484A JPS61152190A JP S61152190 A JPS61152190 A JP S61152190A JP 28170484 A JP28170484 A JP 28170484A JP 28170484 A JP28170484 A JP 28170484A JP S61152190 A JPS61152190 A JP S61152190A
Authority
JP
Japan
Prior art keywords
signal
trigonometric function
output signal
phase
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28170484A
Other languages
Japanese (ja)
Other versions
JPH0319759B2 (en
Inventor
Hidetoshi Ozaki
英俊 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP28170484A priority Critical patent/JPS61152190A/en
Priority to US06/810,067 priority patent/US4721904A/en
Priority to DE198585309519T priority patent/DE186521T1/en
Priority to EP85309519A priority patent/EP0186521B1/en
Priority to DE8585309519T priority patent/DE3584565D1/en
Publication of JPS61152190A publication Critical patent/JPS61152190A/en
Publication of JPH0319759B2 publication Critical patent/JPH0319759B2/ja
Granted legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To lead out an AFC signal, an APC signal, and an ACC signal at a high speed and to simplify the circuit constitution by subjecting an input color burst signal to prescribed arithmetic. CONSTITUTION:The phase of the color burst signal is shifted at 90 deg. or $090 deg. by a -90 deg. phase shifter 4, and the output signal of the phase shifter 4 is divided by the input color burst signal in a divider 5, and the output signal of the divider 5 is subjected to inverse trigonometric function arithmetic by a tan<-1> inverse trigonometric function arithmetic unit 6, and the output signal of the unit 6 is delayed in ahone clock delay circuit 7 by one sampling period, and the difference between te output signal of the unit 6 and that of the delay circuit 7 is operated by an adder 8 to obtain the AFC signal. The output signal of the unit 6 is subjected to trigonometric function arithmetic in an sin trigonometric function arithmetic unit 10, and the output signal of the unit 10 is divided by the input color burst signal or the output signal of the phase shifter 4 in a divider 11 to obtain the ACC signal. The difference of phase between the output signal of the unit 6 and a reference signal is operated by an adder 18 to obtain the APC signal.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はデジタル搬送色信号処理回路に係り、カラーバ
ースト信号からAFC,Ace、APC“に必要な各制
御信号を高速度で得ることができる回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital carrier color signal processing circuit, and more particularly to a circuit that can obtain control signals necessary for AFC, Ace, and APC from color burst signals at high speed. .

手段 第1図中、−90°移相器4はカラーバースト信号の移
相を一90゛移送する移相手段、除算器5は移相器4の
出力信号と入力カラーバースト信号との除算を行なう第
1の除算手段、tan’逆三角関数演算器6は第1の除
算器5の出力信号に逆三角関数演算を行なう逆三角関数
演算手段、1り0ツク遅延回路7は、逆三角間数演算器
6の出力信号を1標本化周期遅延する遅延手段、加算器
8は、逆三角関数演算器6の出力信号と遅延器7の出力
信号との差をとる第1の減算手段、sin三角関数Pi
4絆器10は、逆三角関数演算器6の出力信号に三角関
数演算を行なう三角関数演算手段、除算器11は、三角
関数演算器10の出力信号と上記入力カラーバースト信
号又は上記移相器4の出力信号との除算を行なう第2の
除算手段、加算器18は、上記逆三角関数演算器6の出
力信号と基準信号の位相との差をとる第2の減算手段で
ある。
In FIG. 1, the -90° phase shifter 4 is a phase shifting means for shifting the phase of the color burst signal by -90°, and the divider 5 is for dividing the output signal of the phase shifter 4 and the input color burst signal. The first division means for performing tan' inverse trigonometric function calculation unit 6 is the inverse trigonometric function calculation means for performing inverse trigonometric function calculation on the output signal of the first divider 5; The adder 8 is a delay means for delaying the output signal of the arithmetic operation unit 6 by one sampling period, and the adder 8 is a first subtraction means for taking the difference between the output signal of the inverse trigonometric function operation unit 6 and the output signal of the delay unit 7. Trigonometric function Pi
The four-band unit 10 is a trigonometric function calculation means for performing a trigonometric function calculation on the output signal of the inverse trigonometric function calculation unit 6, and the divider 11 is a trigonometric function calculation unit that performs a trigonometric function calculation on the output signal of the trigonometric function calculation unit 6. The adder 18, which is a second division means that performs division with the output signal of 4, is a second subtraction means that takes the difference between the output signal of the inverse trigonometric function calculator 6 and the phase of the reference signal.

作用 一90°移相器4にてカラーバースト信号の位相を90
°又は−90°移相し、除算器5にて移相器4の出力信
号と入力カラーバースト信号との除算を行ない、tan
’逆三角関数演算器6にて除算器5の出力信号に逆三角
関数演算を行ない、1りOツク遅延回路7にて逆三角関
数演算器6の出力信号を1標本化周期遅延し、加算器8
にて逆三角関数演算器6の出力信号と遅延器7の出力信
号との差をとってAFC信号を得、sin三角関数演算
器10にて逆三角関数演算器6の出力信号に三角関数演
算を行ない、除算器11にて三角関数演算器10の出力
信号と上記入力カラーバースト信号又は上記移相器4の
出力信号との除算を行なってACC信号を得、加算器1
Bにて上記逆三角関数演算器6の出力信号と基準信号の
位相との差をとってAPC信号を得る。
Effect: The phase of the color burst signal is changed to 90° by the 90° phase shifter 4.
The output signal of the phase shifter 4 is divided by the input color burst signal in the divider 5.
'The inverse trigonometric function calculator 6 performs an inverse trigonometric function operation on the output signal of the divider 5, and the 1-O-k delay circuit 7 delays the output signal of the inverse trigonometric function operator 6 by one sampling period, and then adds Vessel 8
, the difference between the output signal of the inverse trigonometric function calculator 6 and the output signal of the delay device 7 is obtained to obtain an AFC signal, and the sine trigonometric function calculator 10 performs a trigonometric function calculation on the output signal of the inverse trigonometric function calculator 6. The output signal of the trigonometric function operator 10 is divided by the input color burst signal or the output signal of the phase shifter 4 in the divider 11 to obtain the ACC signal, and the adder 1
At B, the difference between the output signal of the inverse trigonometric function calculator 6 and the phase of the reference signal is obtained to obtain an APC signal.

実例例 第1図は本発明回路の第1実施例のブロック系統図を示
す。同図において、端子1に入来した搬送色信号は端子
2に入来したカラーパーストゲートパルスにてオンされ
るスイッチ3によりカラーバースト信号のみを抜取られ
る。搬送色信号は一定の標本化周期で標本化されたデジ
タル信号とする。振幅をA1周波数をrc 、位相を0
1とすると、カラーバースト信号は、 a −ASil’l (27t ずCt+01)なる信
号aにて表わされ、−90゛移相器4にてb掌、61c
os(2πfCt+θ1)なる信号すとされる。除算器
5においてa/bが行なわれると、 0−jan (2πfc T十〇、) なる信号Cが得られる。
EXAMPLE FIG. 1 shows a block diagram of a first embodiment of the circuit according to the invention. In the figure, only the color burst signal is extracted from the carrier color signal that has entered terminal 1 by a switch 3 that is turned on by a color burst gate pulse that has entered terminal 2. The carrier color signal is a digital signal sampled at a constant sampling period. Set the amplitude to A1, set the frequency to rc, and set the phase to 0.
1, the color burst signal is represented by a signal a - ASil'l (27t Ct + 01), and -90° phase shifter 4 outputs a signal b, 61c
It is assumed that the signal is os(2πfCt+θ1). When a/b is performed in the divider 5, a signal C is obtained: 0-jan (2πfc T10,).

信号Cはtan’逆三角関数演算器6にてtan−’を
演算されて d=l12π fc t+θi なる信号dとされ、カラー映像信号の標本化周期Tと同
じ周期のクロックで駆動される1クロツク遅延回路7に
て1クロツク遅延されて時間を(を−T)とされ、 d′=2π fc(t−T)+θ1 なる信@d′ とされる。加算器8で信号dと信号d′
との差がとられると(8は実質的には減算器)e雰−2
πfcT中 なる信号eが得られ、これはカラーバースト信号の周波
数rcが一定であれば一定値となる。
The signal C is calculated tan-' by the inverse trigonometric function calculator 6, resulting in a signal d of d=l12π fc t+θi, which is one clock driven by a clock having the same period as the sampling period T of the color video signal. The signal is delayed by one clock in the delay circuit 7, and the time is set to -T, resulting in a signal @d' of d'=2π fc(t-T)+θ1. Signal d and signal d' in adder 8
When the difference between (8 is essentially a subtractor) is taken, e-2
A signal e in πfcT is obtained, which has a constant value if the frequency rc of the color burst signal is constant.

然るに、時刻(t−T)におけるカラーバースト信号の
周波数fcがfc′ に変化したとすると、上記(1)
式は、 e=2π(fc’  −rc )t  −2π fc’
Tとなる。ここで、−2πfc’Tは一定値であり、2
π(rc’ −fC)jは時刻【における周波数fc′
の信号と周波数reの信号との位相変化量を表わしてお
り、信号eは入力カラーバースト信号の周波数に応じた
信号を示している。このため、信号eはAFC信号とし
て用l/1得、端子9を介してAFC回路に供給され、
搬送色信号の周波数が自動的に調節される。
However, if the frequency fc of the color burst signal at time (t-T) changes to fc', the above (1)
The formula is: e=2π(fc'-rc)t-2πfc'
It becomes T. Here, -2πfc'T is a constant value, and 2
π(rc' - fC)j is the frequency fc' at time [
The signal e represents the amount of phase change between the signal at the frequency re and the signal at the frequency re, and the signal e represents a signal corresponding to the frequency of the input color burst signal. Therefore, the signal e is used as an AFC signal by l/1 and is supplied to the AFC circuit via the terminal 9.
The frequency of the carrier color signal is automatically adjusted.

一方、信号dはsin三角関数演算器1oにてsinを
演算されて f −3in  (27r  fc t+θl)なる信
号fとされ、除算器11においてa/bが行なわれると
、 −A なる信号gが得られる。Aは入力カラーバースト信号の
振幅を表わしているので、信号9はACC信号として用
い得、端子12を介してAC,C回路に供給され、搬送
色信号の彩度が自動的に調節される。
On the other hand, the signal d is sin-calculated by the sine trigonometric function calculator 1o to become a signal f of f −3in (27r fc t+θl), and when a/b is performed in the divider 11, a signal g of −A is obtained. can get. Since A represents the amplitude of the input color burst signal, signal 9 can be used as an ACC signal and is fed via terminal 12 to the AC,C circuit to automatically adjust the saturation of the carrier color signal.

ところで、13はROM17を有する■COで、基準信
号源である。ROM17には、アナログ処理のものであ
れば第2図示の振幅データがストアされているが、本実
施例では第3図示の位相データがストアされている。1
クロック遅延回路16は搬送色信号の標本化クロックと
同じクロックで駆動される構成とされている。
By the way, 13 is a CO having a ROM 17, which is a reference signal source. In the ROM 17, the amplitude data shown in the second figure is stored if the data is analog processed, but in this embodiment, the phase data shown in the third figure is stored. 1
The clock delay circuit 16 is configured to be driven by the same clock as the sampling clock of the carrier color signal.

端子14に入来した出力すべき基準信号発振周波数r6
に応じたデータhは加算器15.1クロック遅延回路1
6にて構成される回路にて80Mアドレス1IIIII
Ill信号iとされ、ROM17に供給される。この場
合、1りOツク遅延回路16の出力ではデータhが1標
本化周期毎に汀線されるが、加算器15はそのビット長
は有限であるので一定周期毎にオーバフローを生じ、R
OMアドレス制御信号iのデータの大きさは第4図示の
如くになる。
Reference signal oscillation frequency r6 that has entered the terminal 14 and should be output
The data h according to the adder 15.1 clock delay circuit 1
80M address 1III with a circuit composed of 6
The Ill signal i is supplied to the ROM 17. In this case, at the output of the 1-O clock delay circuit 16, the data h is shorelined every sampling period, but since the bit length of the adder 15 is finite, overflow occurs at every fixed period, and R
The data size of the OM address control signal i is as shown in FIG.

ROM17にアドレス制御信号:が供給されることによ
り、ROM17のアドレスがクロックに応じて順次更新
され、ROM17よりO〜2πの位相データjが取出さ
れる。基準信号の位相をθ2とすると、時刻tの位相デ
ータjはj=!2π f、 t+θ2 と表わされる。AFCにより入力カラーバースト信号の
周波数がf、に制御されているとすれば、信号dは d−2π1.1+θ1 である。加算器18において信号dと信号jとの差がと
られると(18は実質的には減算器)、k=θ2−θ電 なる信号kが得られる。信号には基準信号と入力カラー
バースト信号との位相差を表わしているので、信号には
APC信号として用い得、端子19を介してAPC回路
に供給され、搬送色信号の位相が自動的に調節される。
By supplying the address control signal : to the ROM 17, the address of the ROM 17 is sequentially updated in accordance with the clock, and phase data j of O to 2π is taken out from the ROM 17. If the phase of the reference signal is θ2, the phase data j at time t is j=! It is expressed as 2π f, t+θ2. If the frequency of the input color burst signal is controlled by AFC to f, then the signal d is d-2π1.1+θ1. When the difference between the signal d and the signal j is taken in the adder 18 (18 is essentially a subtracter), a signal k is obtained, where k=θ2−θ. Since the signal represents the phase difference between the reference signal and the input color burst signal, it can be used as an APC signal and is fed to the APC circuit via terminal 19, so that the phase of the carrier color signal is automatically adjusted. be done.

第5図は本発明回路の第2実施例のブロック系統図を示
し、同図中、第1図と同一構成部分、同一信号には夫々
同一番号、同一符号を付す。このものは、基準信号周波
数to と標本化周波数rsとの間に、 fs=N  −fe なる関係(但し、Nは3以上の整数)がある場合に適用
される。
FIG. 5 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components and signals as in FIG. 1 are designated by the same numbers and symbols, respectively. This is applied when there is a relationship fs=N-fe (where N is an integer of 3 or more) between the reference signal frequency to and the sampling frequency rs.

端子20に入来した標本化周波数rsはN進カウンタ2
1にてNカウントされてROM17に供給され、これに
より、ROM17はNカウント毎にアドレスを更新され
てこのアドレスに応じた0〜2πの位相データが取出さ
れる。この位相データは減算器18に供給され、上記第
1実施例と同様に位相差(θ1−θ2)が取出される。
The sampling frequency rs input to the terminal 20 is input to the N-ary counter 2.
1 is counted by N and supplied to the ROM 17, whereby the address of the ROM 17 is updated every N counts and phase data of 0 to 2π corresponding to this address is taken out. This phase data is supplied to the subtracter 18, and the phase difference (θ1-θ2) is extracted as in the first embodiment.

なお、基準信号周波数f・と標本化周波数rsとの簡に fs−4M・ 「・ なる関係(但し、Mは1以上の整数)がある場合第1図
示、第5図示の一90゛移相器4として入力信号をMク
ロック遅延させる遅延回路を用いてもよい。
Note that if there is a relationship between the reference signal frequency f and the sampling frequency rs that is simply fs-4M (where M is an integer of 1 or more), the phase shift of 190° as shown in Figures 1 and 5 is applied. As the device 4, a delay circuit that delays the input signal by M clocks may be used.

又、−90゛移相器4、除算器5.11、加算器8.1
8、tan’逆三角関数演算器6、sin三角関数演算
器10.1クロック遅延回路7.16等の各回路にはR
OMによる関数テーブルを用いてもよい。
Also, -90゛ phase shifter 4, divider 5.11, adder 8.1
8, tan' inverse trigonometric function operator 6, sin trigonometric function operator 10.1, clock delay circuit 7.16, and other circuits have R.
A function table based on OM may also be used.

なお、除算器5における除算をb/aにした場合、演算
器6をcot’逆三角関数演算器にすれば同様の結果を
得ることができる。
Note that when the division in the divider 5 is b/a, a similar result can be obtained by using a cot' inverse trigonometric function calculator as the calculator 6.

又、演算器6を−tan−’逆三角関数演算器、演算器
10を−sin三角閤三角算数演算器も同様の結果を得
ることができる。
Furthermore, similar results can be obtained by using a -tan-' inverse trigonometric function arithmetic unit as the arithmetic unit 6 and a -sin trigonometric arithmetic arithmetic unit as the arithmetic unit 10.

又、演算器6,10のいずれか一方の符号を負とした場
合には出力Qの符号が上記の場合と反転。
Furthermore, when the sign of either the arithmetic units 6 or 10 is negative, the sign of the output Q is inverted from the above case.

する。do.

又、除算器11を信号f、bの除算を行なうようにする
場合、演算器10をCOS三角関数演算器にすれば同様
の結果を得ることができる。
Furthermore, when the divider 11 is configured to divide the signals f and b, a similar result can be obtained by using a COS trigonometric function unit as the arithmetic unit 10.

又、−90゛移相器4の代りに+90°移相器を用いて
もよく、90°移相器、−90°移相器としてはヒルベ
ルト・フィルタを用いればよい。
Further, a +90° phase shifter may be used instead of the -90° phase shifter 4, and a Hilbert filter may be used as the 90° phase shifter and the -90° phase shifter.

発明の効果 本発明回路は、一定の標本化周期で標本化された搬送色
信号から抜取られたカラーバースト信号の位相を90°
又は−90°移相する移相器と、移相器の出力信号と入
力カラーバースト信号との除算を行なう第1の除算器と
、第1の除算器の出力信号に逆三角関数演算を行なう逆
三角関数演算器と、逆三角関数演算器の出力信号を1標
本化周期遅延する遅延器と、逆三角関数演算器の出力信
号と遅延器の出力信号との差をとる第1の減算器と、逆
三角関数演算器の出力信号に三角関数演算を行なう三角
関数演算器と、三角関数演算器の出力信号と上記入力カ
ラーバースト信号又は上記移相器の出力信号との除算を
行なう第2の除算器と、上記逆三角関数演算器の出力信
号と基準信号の位相との差をとる第2の減算器とにて構
成したため、AFC信号、APC信号、ACC信号を夫
々^速度に得ることができ、この場合、位相比較器を用
いていないので回路を簡単に構成し得、又、温度変化、
経時変化等の影響を受けにくく、又、回路をIC化し易
く、又、入力カラーバースト信号の波数が少なくても確
実に制御信号を得ることができる等の特長を有する。
Effects of the Invention The circuit of the present invention changes the phase of a color burst signal extracted from a carrier color signal sampled at a constant sampling period by 90°.
or a phase shifter that shifts the phase by -90°, a first divider that divides the output signal of the phase shifter and the input color burst signal, and performs an inverse trigonometric function operation on the output signal of the first divider. an inverse trigonometric function operator, a delay device that delays the output signal of the inverse trigonometric function operator by one sampling period, and a first subtractor that takes the difference between the output signal of the inverse trigonometric function operator and the output signal of the delay device. a trigonometric function calculator that performs trigonometric function calculations on the output signal of the inverse trigonometric function calculator; and a second trigonometric function calculator that performs division of the output signal of the trigonometric function calculator and the input color burst signal or the output signal of the phase shifter. Since it is composed of a divider and a second subtracter that takes the difference between the output signal of the inverse trigonometric function calculator and the phase of the reference signal, it is possible to obtain the AFC signal, APC signal, and ACC signal at respective speeds. In this case, since no phase comparator is used, the circuit can be easily configured, and it is also possible to
It has features such as being less susceptible to changes over time, easy to integrate the circuit into an IC, and being able to reliably obtain a control signal even if the input color burst signal has a small wave number.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明回路の第1実施例のブロック系統図、第
2図及び第3図は夫々アナログ処理の場合及び本実施例
の場合におけるROMのストアデータの図、第4図はR
OMのアドレス制御信号の図、第5図は本発明回路の第
2実施例のブロック系統図である。 1・・・搬送色信号入力端子、2・・・カラーパースト
ゲートパルス入力端子、3・・・スイッチ、4・・・=
90°移相器、5.11・・・除算器、6・・・jan
−’逆三角関数演算器、7.16・・・1クロック遅延
回路、8.15.18・・・加算器、9・・・AFC信
号出力端子、10・・・sin三角関数演算器、12・
・・ACC信号出力端子、13・・−VCO114・・
・データ入力端、17・・・ROM、19・・・APC
信号出力端子、20・・・標本化周波数入力端子、21
・・・N進カウンタ。 第1図 第4図
FIG. 1 is a block system diagram of the first embodiment of the circuit of the present invention, FIGS. 2 and 3 are diagrams of ROM store data in the case of analog processing and in the case of this embodiment, respectively, and FIG. 4 is a diagram of the R
FIG. 5, which is a diagram of the address control signal of the OM, is a block system diagram of a second embodiment of the circuit of the present invention. 1...Carrier color signal input terminal, 2...Color burst gate pulse input terminal, 3...Switch, 4...=
90° phase shifter, 5.11...divider, 6...jan
-' Inverse trigonometric function calculator, 7.16... 1 clock delay circuit, 8.15.18... Adder, 9... AFC signal output terminal, 10... Sin trigonometric function calculator, 12・
...ACC signal output terminal, 13...-VCO114...
・Data input terminal, 17...ROM, 19...APC
Signal output terminal, 20... Sampling frequency input terminal, 21
...N-ary counter. Figure 1 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)一定の標本化周期で標本化された搬送色信号から
抜取られたカラーバースト信号の位相を90°又は−9
0°移相する移相器と、該移相器の出力信号と該入力カ
ラーバースト信号との除算を行なう第1の除算器と、該
第1の除算器の出力信号に逆三角関数演算を行なう逆三
角関数演算器と、該逆三角関数演算器の出力信号を1標
本化周期遅延する遅延器と、該逆三角関数演算器の出力
信号と該遅延器の出力信号との差をとる第1の減算器と
、該逆三角関数演算器の出力信号に三角関数演算を行な
う三角関数演算器と、該三角関数演算器の出力信号と上
記入力カラーバースト信号又は上記移相器の出力信号と
の除算を行なう第2の除算器と、上記逆三角関数演算器
の出力信号と基準信号の位相との差をとる第2の減算器
とよりなることを特徴とするデジタル搬送色信号処理回
路。
(1) The phase of the color burst signal extracted from the carrier color signal sampled at a constant sampling period is 90° or -9
A phase shifter that shifts the phase by 0°, a first divider that divides the output signal of the phase shifter and the input color burst signal, and an inverse trigonometric function operation on the output signal of the first divider. an inverse trigonometric function operator, a delay device that delays the output signal of the inverse trigonometric function operator by one sampling period; 1, a trigonometric function calculator that performs a trigonometric function calculation on the output signal of the inverse trigonometric function calculator, and an output signal of the trigonometric function calculator and the input color burst signal or the output signal of the phase shifter. A digital carrier chrominance signal processing circuit comprising: a second divider that performs division; and a second subtracter that takes the difference between the output signal of the inverse trigonometric function calculator and the phase of the reference signal.
(2)該移相器、第1及び第2の除算器、逆三角関数演
算器、三角関数演算器、遅延器、第1及び第2の減算器
は、ROMによる関数テーブルを用いてなることを特徴
とする特許請求の範囲第1項記載のデジタル搬送色信号
処理回路。
(2) The phase shifter, the first and second dividers, the inverse trigonometric function operator, the trigonometric function operator, the delay unit, and the first and second subtractors are constructed using function tables based on ROM. A digital carrier color signal processing circuit according to claim 1, characterized in that:
JP28170484A 1984-12-25 1984-12-25 Digital chrominance signal processing circuit Granted JPS61152190A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP28170484A JPS61152190A (en) 1984-12-25 1984-12-25 Digital chrominance signal processing circuit
US06/810,067 US4721904A (en) 1984-12-25 1985-12-17 Digital phase difference detecting circuit
DE198585309519T DE186521T1 (en) 1984-12-25 1985-12-30 DIGITAL SWITCHING TO DISPLAY THE PHASE DIFFERENCE.
EP85309519A EP0186521B1 (en) 1984-12-25 1985-12-30 Digital phase difference detecting circuit
DE8585309519T DE3584565D1 (en) 1984-12-25 1985-12-30 DIGITAL CIRCUIT TO DISPLAY THE PHASE DIFFERENCE.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28170484A JPS61152190A (en) 1984-12-25 1984-12-25 Digital chrominance signal processing circuit

Publications (2)

Publication Number Publication Date
JPS61152190A true JPS61152190A (en) 1986-07-10
JPH0319759B2 JPH0319759B2 (en) 1991-03-15

Family

ID=17642813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28170484A Granted JPS61152190A (en) 1984-12-25 1984-12-25 Digital chrominance signal processing circuit

Country Status (1)

Country Link
JP (1) JPS61152190A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130787A (en) * 1989-04-26 1992-07-14 Victor Company Of Japan, Ltd. Color signal processing circuit with residue phase error correction
US5185657A (en) * 1989-04-26 1993-02-09 Victor Company Of Japan, Ltd. Color signal processing circuit with residual phase error correction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130787A (en) * 1989-04-26 1992-07-14 Victor Company Of Japan, Ltd. Color signal processing circuit with residue phase error correction
US5185657A (en) * 1989-04-26 1993-02-09 Victor Company Of Japan, Ltd. Color signal processing circuit with residual phase error correction

Also Published As

Publication number Publication date
JPH0319759B2 (en) 1991-03-15

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