JPS61150241A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61150241A JPS61150241A JP59272222A JP27222284A JPS61150241A JP S61150241 A JPS61150241 A JP S61150241A JP 59272222 A JP59272222 A JP 59272222A JP 27222284 A JP27222284 A JP 27222284A JP S61150241 A JPS61150241 A JP S61150241A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealed case
- sealed
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、例えば半導体装置の製造工程において、ポ
ンディグ接続の施された半導体ペレットの周囲を樹脂封
止し、ＬＳＩもしくはフォトカプラ等の樹脂封止型の高
集積度ＩＣや光半導体装置を製造する際に使用される半
導体装置の製造方法に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to resin-sealing the periphery of a semiconductor pellet with bonding connections, for example, in the manufacturing process of a semiconductor device, and resin-sealing an LSI or a photocoupler, etc. The present invention relates to a method for manufacturing a semiconductor device used in manufacturing a type of highly integrated IC or an optical semiconductor device.
〔発明の技術的背Ｗ４］
一般に、ＬＳＩ等の樹脂封止型半導体装置は、第４図に
示すように構成されている。すなわち、まず集積回路網
の形成された半導体ベレット１１をリードフレームのペ
レットベッド１２上に載置貼着する。次に、半導体ペレ
ット１１の回路網電極となるポンディングパッド部とリ
ードフレームの各内部リード１３ａ、１３ｂの先端部と
を、ボンディングワイヤ１４ａ、１４ｂにより接続する
。そして、このボンディングワイヤ１４ａ、１４ｂおよ
び上記内部リード１３ａ、１３ｈを含む上記半導体ベレ
ット１１の周囲を、エポキシ等でなる樹脂封止ケース１
５により封止する。[Technical Background of the Invention W4] Generally, a resin-sealed semiconductor device such as an LSI is configured as shown in FIG. That is, first, a semiconductor pellet 11 on which an integrated circuit network is formed is placed and adhered onto a pellet bed 12 of a lead frame. Next, the bonding pad portion of the semiconductor pellet 11, which becomes the circuit network electrode, and the tip of each internal lead 13a, 13b of the lead frame are connected by bonding wires 14a, 14b. A resin sealing case 1 made of epoxy or the like is placed around the semiconductor bullet 11 including the bonding wires 14a, 14b and the internal leads 13a, 13h.
5 for sealing.
この場合、内部リード１３ａ、１３ｂから内側の空間を
金型（図示せず）等によって囲み、この金型内に熱によ
り溶かされる溶融樹脂１６を流し込み充填冷却して樹脂
封止を施している。In this case, the space inside from the internal leads 13a and 13b is surrounded by a mold (not shown) or the like, and the molten resin 16 melted by heat is poured into the mold, filled and cooled to perform resin sealing.
［青票技術の問題点］
しかし、このようにして製造される樹脂封止型の半導体
装置では、樹脂封止ケース１５は単なる工ボキシ等の樹
脂でなるものであるため、外部からの電気的ノイズや外
乱光等を通してしまう。このため、実際の使用時におい
て、隣接する機器や周囲の環境による影響を受けやすく
、装置組込み時において、ユーザ側にて種々の工夫をし
ているのが現状である。また、特に光半導体装置の樹脂
封止ケースに白色樹脂を用いた場合には、上記外乱光に
よる影響は極めて大きく、誤動作を招く恐れがある。[Problems with the blue slip technology] However, in the resin-sealed semiconductor device manufactured in this way, the resin-sealed case 15 is simply made of a resin such as a plastic box, so electrical It allows noise, ambient light, etc. to pass through. For this reason, during actual use, it is susceptible to the effects of adjacent equipment and the surrounding environment, and the current situation is that users must take various measures when incorporating the device into the device. Moreover, especially when white resin is used for the resin-sealed case of an optical semiconductor device, the influence of the above-mentioned disturbance light is extremely large, and there is a risk of malfunction.
［発明の目的］
この発明は上記のような問題点に鑑みなされたもので、
外部からの電気的ノイズや外乱光等により！！彰菅を受
けることなく、誤動作発生の恐れを無くすことができる
ようになる半導体装置の製造方法を提供することを目的
とする。[Object of the invention] This invention was made in view of the above problems.
Due to external electrical noise or disturbance light! ! It is an object of the present invention to provide a method for manufacturing a semiconductor device that can eliminate the risk of malfunctions without having to undergo any formalities.
［発明の概要］
すなわちこの発明に係わる半導体装置の製造方法は、内
部リードおよびボンディングワイヤを含む半導体素子の
周囲を樹脂封止し、この樹脂封止ケースの上記内部リー
ドに連続する外部リードが突設される表面以外の他の表
面にのみ金属？ｅｌＳを形成するようにしたものである
。[Summary of the Invention] That is, the method for manufacturing a semiconductor device according to the present invention includes sealing the periphery of a semiconductor element including internal leads and bonding wires with a resin, and protruding external leads that are continuous with the internal leads of the resin-sealed case. Metal only on other surfaces than the one where it is installed? elS is formed.
［発明の実施例］ 以下図面によりこの発明の一実施例を説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.
第１図はその製造工程を示すもので、まずは、前記第４
図にて示した半導体装置と同様にして、例えば半導体素
子の製造過程を経て集積回路網の形成された半導体ベレ
ット１１を、金属板に打抜き加工等を施して形成された
リードフレームのペレットベッド１２上に載置貼着する
。次に、上記半導体ベレット１１の回路網Ｎ極となるパ
ッド部と上記リードフレームの内部リード１３ａ、１３
ｂとを、ボンディングワイヤ１４ａ、１４ｂによりボン
ディング接続する。そして、上記内部リード１３ａ、１
３ｂおよびボンディングワイヤ１４ａ、１４ｂを含む半
導体ベレット１１の周囲空間を、図示しない樹脂封止金
型により囲み、この金型内に熱により溶がされるエポキ
シ系の溶融樹脂１６を注入充填する。これにより、半導
体ペレット１１の樹脂封止が施されるもので、この後の
冷却過程を経て樹脂封止ケース１５を形成する０次に、
上記樹脂封止ケース１５の両側面部、っまり上記内部リ
ード１３ａ、１３ｂ １．：連続する外部り一ド１７ａ
、１７ｂが突設される表面部１８ａ、１８ｂを、リード
フレーム保護用の冶具１９によりカバーする。そして、
この冶具１９によりカバーされる樹脂封止ケース１５の
両側表面部１８ａ、１８ｂ以外の他の表面部２０ａ、２
０ｂ 、つまりケース１５の上下面部のみに、アルミニ
ウム等による金属被１１２．１ａ、２１ｂを蒸着形成す
る。Figure 1 shows the manufacturing process.
Similar to the semiconductor device shown in the figure, a pellet bed 12 of a lead frame is formed by punching a semiconductor pellet 11 on which an integrated circuit network is formed, for example, from a metal plate through the manufacturing process of a semiconductor element. Place and paste on top. Next, the pad portion of the semiconductor pellet 11 serving as the N pole of the circuit network and the internal leads 13a, 13 of the lead frame are connected.
b are bonded and connected by bonding wires 14a and 14b. Then, the internal leads 13a, 1
3b and the bonding wires 14a, 14b are surrounded by a resin sealing mold (not shown), and a molten epoxy resin 16 melted by heat is injected and filled into the mold. As a result, the semiconductor pellet 11 is resin-sealed, and the resin-sealed case 15 is formed through the subsequent cooling process.
Both side surfaces of the resin-sealed case 15, including the internal leads 13a and 13b 1. :Continuous external direction 17a
, 17b are covered with a jig 19 for protecting the lead frame. and,
Surface portions 20a and 2 other than both side surface portions 18a and 18b of the resin-sealed case 15 covered by this jig 19
0b, that is, only on the upper and lower surfaces of the case 15, metal coverings 112.1a and 21b made of aluminum or the like are formed by vapor deposition.
すなわちこのような製造工程においては、第２図に示す
ように、樹脂封止ケース１５の上下面側表面部２０ａ、
２０ｂのみが金属被膜により覆われた半導体装置が構成
されるようになる。これにより、外部からの電気的ノイ
ズおよび外乱光等は、矢印ＡおよびＢで示すように、そ
のほとんどが上記金属被膜２１ａ、２１ｂにより遮蔽さ
れるようになり、樹脂封止ケース１５を介して半導体素
子１１の電気的特性に悪影響を及ぼすことはない。した
がって、例えば隣接する機器からの電気的ノイズや外乱
光を原因とする樹脂封止型半導体装置の特性悪化および
光半導体装置の誤動作は完全に防止されるようになり、
信頼性の向上を図ることができる。That is, in such a manufacturing process, as shown in FIG.
A semiconductor device is now constructed in which only 20b is covered with a metal film. As a result, most of the electrical noise and disturbance light from the outside are shielded by the metal coatings 21a and 21b, as shown by arrows A and B, and the semiconductor The electrical characteristics of the element 11 are not adversely affected. Therefore, for example, deterioration of the characteristics of resin-sealed semiconductor devices and malfunctions of optical semiconductor devices caused by electrical noise or ambient light from adjacent equipment can be completely prevented.
Reliability can be improved.
尚、上記実施例において樹脂封止ケースの表面に形成し
た金属被膜を、第３図に示すように、接地端子に対応す
る外部リードＧＮＤに電気的に導通させれば、上記ノイ
ズおよび外乱光はさらに効果的に遮蔽されるようになる
。In addition, if the metal film formed on the surface of the resin-sealed case in the above embodiment is electrically connected to the external lead GND corresponding to the ground terminal as shown in FIG. 3, the above noise and ambient light can be eliminated. It will be more effectively shielded.
［発明の効果］
以上のようにこの発明によれば、樹脂封止ケースの外部
リードが突設される表面以外の他の表面にのみ金属被膜
を形成したので、外部からの電気的ノイズや外乱光等に
より影響を受けることなく、誤動作の発生を防止するこ
とが可能となる半導体装置の製造方法を提供できる。[Effects of the Invention] As described above, according to the present invention, the metal coating is formed only on the surface other than the surface on which the external leads of the resin-sealed case are protruded, so that electrical noise and disturbances from the outside are prevented. It is possible to provide a method for manufacturing a semiconductor device that can prevent malfunctions without being affected by light or the like.
第１図はこの発明の一実施例に係わる半導体装置の製造
工程を示す断面構成図、第２図は上記製造工程を経て製
造された樹脂封止型半導体装置を示す断面構成図、第３
図はこの発明の他の実施例を示す図、第４図は従来の樹
脂封止型半導体装置６一
を示す断面構成図である。
１１・・・半導体ベレット、１２・・・ペレットベッド
、１３ａ、１３ｂ・・・内部リード、１４ａ、１４ｂ・
・・ボンディングワイヤ、１５・・・樹脂封止ケース、
１７ａ、１７ｂ・・・外部リード、１９ａ、１９ｂ−・
・リードフレーム保護用治具、２１ａ。
２１ｂ−・・金属被膜。FIG. 1 is a cross-sectional configuration diagram showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional configuration diagram showing a resin-sealed semiconductor device manufactured through the above manufacturing process, and FIG.
The figure shows another embodiment of the present invention, and FIG. 4 is a cross-sectional configuration diagram showing a conventional resin-sealed semiconductor device 61. DESCRIPTION OF SYMBOLS 11... Semiconductor pellet, 12... Pellet bed, 13a, 13b... Internal lead, 14a, 14b.
...Bonding wire, 15...Resin sealing case,
17a, 17b...external leads, 19a, 19b-...
- Lead frame protection jig, 21a. 21b--Metal coating.
Claims (1)
子電極と内部リードとをボンディング接続し、この内部
リードおよびボンディングワイヤを含む上記半導体素子
の周囲を樹脂封止する手段と、この樹脂封止手段により
形成された樹脂封止ケースの上記内部リードに連続する
外部リードが突設される表面以外の他の表面にのみ金属
被膜を形成する手段とを具備したことを特徴とする半導
体装置の製造方法。A means for bonding a semiconductor element electrode placed on a pellet bed of a lead frame and an internal lead, and sealing the periphery of the semiconductor element including the internal lead and bonding wire with a resin, and forming by the resin sealing means. a method for manufacturing a semiconductor device, comprising means for forming a metal coating only on a surface other than a surface on which an external lead continuous with the internal lead of the resin-sealed case is protruded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272222A JPS61150241A (en) | 1984-12-24 | 1984-12-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272222A JPS61150241A (en) | 1984-12-24 | 1984-12-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61150241A true JPS61150241A (en) | 1986-07-08 |
Family
ID=17510813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59272222A Pending JPS61150241A (en) | 1984-12-24 | 1984-12-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017168704A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
1984
- 1984-12-24 JP JP59272222A patent/JPS61150241A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017168704A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN107204312A (en) * | 2016-03-17 | 2017-09-26 | 东芝存储器株式会社 | The manufacture method and semiconductor device of semiconductor device |
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