JPS61150199A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To restrict a parasitic thyristor effect and perform a stable writing operation by impressing a high voltage generated in a writing terminal during writing to a non-selected word line. CONSTITUTION:By connecting a restricted voltage impressing circuit 12 to a writing terminal,an electric potential of a word line in a non-selected condition is raised above the potential of a digit line. Accordingly, a circuit 12 operates, but since in resistances R1M, R2M a high resistance is selected, an electric current scarcely flows, a lowering of a voltage becomes a sum of a voltage between a collector and an emitter of a pnp FET Q1M, a voltage between the emitter and a base of an npn FET Q2M, a forward direction voltage of a diode D1M, a word line W1 has a high voltage, and an operation of a parasitic thyristor comprising a written cell and a writing cell in the same word line W1 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically writable read-only semiconductor memory device.

[Conventional technology]

In general, electrically writable semiconductor memory devices use NPN (npn) 9 transistors with open bases as memory cells (hereinafter referred to as cells), and the digit line is connected to the word line from the side connected to the digit line. A current of around 100 m is applied to the rectifier side (normally = 0 that shares the rector area), and the cells are joined together by two ivy paces! When connected, more information is written.

This (MF-included creation involves high voltage, so various parasitic effects occur.Among them, parasitic PNP), the transistor and parasitic N
Among the parasitic thyristors configured with transistors (pn, ), the following two parasitic thyristors that have an adverse effect on writing will be described.

The first parasitic thyristor consists of a written cell and an unwritten cell on the same word line. In FIG. 5, it is assumed that the digit line and word line Wl are selected to write into the cell M. At this time, the unselected word NWt includes pnp)9 registers Q and npn
) Thungister Q, a parasitic thyristor is formed.

Here, Ql is the base of cell M, word line W1. A pnp transistor whose emitter, base, and collector are the bases of cells M and l, respectively; Qt is the emitter of cell MB;
An npn (npn) transistor whose base and word line W□ are the emitter, base, and collector, respectively. Since the word driver WD is not selected, the potential of the word line WL is about 4.
4V, while digit line D! Since the write current is flowing, the voltage rises to about 16V. Is the current charging the capacitance C between the ninth word line W1 and the substrate pnp? flows as a pace current in transistor Q1, pnp)? transistor Q is turned on, and the parasitic thyristors consisting of transistor Q1 (pnp) and transistor Q (npn) operate. Then, a part of the write current from the debit line passes through the parasitic current path of parasitic thyristor→cell MH→word driver WD, and a sufficient write current cannot be supplied to the cell Mn to which data is to be written.

The second parasitic thyristor consists of a written cell between and on one of the two word lines. In FIG. 7, select the digit line and word line w8 and select the cell M21.
shall be written. If there is already a written cell Mu on the unselected word line Wl, as shown in FIG. 8, the word lines Wt, W! In between are pnp) transistors Q, and npn
) A parasitic thyristor consisting of transistor Q4 is created. Here, J)nJ)) transistor Q3 is cell M11
The base, word mw, and substrate are the emitter, base, and collector, respectively, and the npn) transistor Q1 is word mw.
The Ws, the board, and the word MW are used as the collector, the base, and the workpiece, respectively. When the digit line is carrying a write current, it rises to about 16V as in the previous example. Therefore, in FIG. 8, the charging current of the parasitic capacitance C between the word line W1 and the substrate becomes a current of the pnp transistor Q, flows as a collector current of about 1 mA, and is absorbed into the collector, that is, the substrate. Since the parasitic resistance r of this current path is about 2Ω, the pace potential of the npn transistor Q4 rises to 1mA×2Ω−2V. On the other hand, word line W! Since it is in the selected state, the potential is about 1V, and the npn) transistor Q.

A forward bias of 2V-IV=IV is applied between the base and emitter of. Therefore, transistor Q4 (npn) is turned on, and the parasitic thyristor consisting of transistors Q, , Q operates, and a part of the write current from the digit line flows through the parasitic thyristor, causing the cell Mt to be written to.
1 will not be supplied with sufficient write current.

[Problem that the invention seeks to solve]

In this way, in the conventional electrically writable read-only semiconductor memory device TLC, the parasitic thyristor configured in parallel with the original write path operates during writing, so There was a problem in that a suitable write current was not supplied and cells could not be written.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electrically writable read-only semiconductor memory device that can perform stable writing without operating a parasitic thyristor during a writing operation.

[Means for solving problems]

The semiconductor memory device of the present invention suppresses the application of the voltage generated at the write terminal to unselected word lines during writing in a semiconductor memory device in which more than K amount of information is written by flowing a current from the write terminal to destroy the junction. It has a voltage application circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing essential parts of a first embodiment of the present invention. In FIG. 1, for convenience of explanation, the write circuit 11 is
According to the present invention, there is only one write terminal (usually an output terminal) 0, a digit line DID, and two terminals 12. The pnp) transistor QIM and the npn) transistor QtMK constitute a thyristor, and a diode DoM is included to provide a trigger current. This diode DoM breaks down when a high voltage is applied to the emitter of the pnp transistor QIM, and operates by supplying a pace current to the npn) transistor (hm). It becomes inactive when the voltage is removed.

This thyristor is connected from the emitter of transistor QIM to resistor RIM, diode DIMtM to word line W.
Connect to 1. The same applies to other word lines. Note that the word driver WD s in the first embodiment
, WD x is shown in FIG. 2, which is commonly used. In FIG. 2, the npn) transistor Qzm is on when the word line is selected and off when the word line is not selected, and the resistor R1! , diode I)zt
The voltage is raised to near the stain source voltage Vcc.

Referring again to FIG. 1, the circuit connected to the digit line D3 is selected (npn) by the decoder (not shown) and the trigger circuit 13, and a pace current is supplied to the transistor Q. )Write terminal 0 to 100mA
It is assumed that a certain amount of current is flowing. Depending on the write specifications, write terminal 0 rises to a maximum of 20V. Digit line D! is a diode Dc, a pnp transistor Qs
Collector-emitter voltage of w+npn) transistor Q2w.

The voltage rises to 16V by subtracting the potential drop due to the voltage of the emitter-pace junction of Q3w, IV+0.4V+1.4V+1.2V=4V. Next, consider the potential of the word line. It is assumed that word line W is not selected and word line W is selected. In the absence of the suppression voltage application circuit 12 according to the present invention, the potential of the word line W1 changes from the power supply voltage VCC to the resistance R+! in the word driver circuit in FIG. 8. The voltage is about 4.4V, which is drawn by the diode D□. Therefore, in the conventional method, pnp in FIG.
) transistor Q is turned on and the parasitic thyristor operates, pnp in Figure 8) transistor Q4 is turned on due to leakage current between the emitter and collector of transistor Q3 → pnp) transistor Q is turned on → thyristor operates A parasitic current path was formed.The suppressing voltage applying circuit 12 according to the present invention functions to raise the potential of a word line in a non-selected state to a level higher than the potential of a digit line by being connected to a write terminal. As mentioned above, the write terminal 0 rises by a maximum of 20V-1, and when the potential drop IV caused by the diode DCI/C is subtracted, the emitter of the transistor Q1w becomes 19V. Therefore, the suppression voltage application circuit 12 operates, but since the resistors R,..., R1M are selected to have high resistance (for example, 20Ω), almost no current flows, and the voltage drop is caused by the voltage drop caused by the PnP transistor QI.
M's; rector-emitter voltage e npn ): ynister Q! Emitter-to-pace voltage of M, diode DI
The sum of the forward voltages of M! 0.3V+0.8V+0.
6V=1.7V. In the end, the potential of word line W is 19
It can be raised to V-1,7V-17,3V. Therefore, as shown in FIG. 6, the operation of a parasitic thyristor consisting of a written cell and an unwritten cell on the same word line W can be prevented. That is, in FIG. 6, the emitter potential of the pnp transistor Q is on the digit line.

16V, the pace potential is word line W, potential 17.3■
Therefore, the pnp transistor Q1 is never turned on. Therefore, all the write current can be passed through the cell M0. In this case, the operating current of the thyristor flows through the selected word line W, the suppression voltage application circuit 2, the resistor R, and the diode D0, but this operating current is negligible as described above. It's small so it won't affect anything else.

On the other hand, as shown in FIG. 8, the same can be said of the parasitic thyristor 9 between the two word lines W1°W and the written cell on one of the word lines W1. That is, in FIG. 8, the digit line rises to 16V, but the potential of the word line Wl is 173V, so the charging current of the parasitic capacitance C between the word line W1 and the substrate does not flow, and the pn
p)? The trigger current of the transistor Q3 can be eliminated. Therefore, transistor Q! pnp) and transistor Q can be prevented from turning on. , Q+) leakage of the write current of the parasitic thyristor can be eliminated.

FIG. 3 is a circuit diagram showing a main part of the embodiment of the present invention shown in FIG. 2. In this embodiment, in the first embodiment shown in FIG. 1, a diode DIM and a resistor R1M for connecting the word lines W, , W, to a high voltage are inserted into the word driver WD, /. It is. The word driver circuit is shown in FIG. In FIG. 4, the diode D4m and the resistor R41 correspond to the above glue, M, and RIM.

Resistor R4, diode D48 is npn during reading.
)') It is for supplying the collector current of the transistor Q41. Terminal MH is the suppression voltage application circuit 1 in FIG.
20npn transistor Q! It is connected to the emitter of M.

The operation is exactly the same as in the first embodiment.

Note that it is clear that this circuit does not interfere with normal read operations.The effect of the OC invention has been explained above in detail.According to the present invention, since it has the above means, it is possible to By applying the high voltage generated at the write terminal to the unselected word il[K,
An electrically writable read-only semiconductor memory device is obtained in which parasitic thyristor effects are suppressed and stable write operations can be performed.

[Brief explanation of the drawing]

FIG. 1 shows the main part of the XO embodiment of the present invention, and FIG.
The figure shows a circuit diagram of the word driver in FIG. 3, and FIGS. 5 and 6, and FIGS. 7 and 8 respectively show a parasitic thyristor 11, write circuit, 12, etc. in a conventional semiconductor memory circuit. ...Suppression voltage application circuit, 13...
・Trigger circuit, Dl sDl... digit line,
Da, D,, D IM,
D, M, D, l, D,, , D,,
[D4j...Diode, MH, -...Terminal, 0
・・・・・・Write terminal, QIM* Qtws” Pn
P) 77 jista, Q1MIQ*wa Qtws Q
41 rQ4r'npn) range meta) B+, M,
R,,,R,1,B+,! , B+4. - resistance, v c
e ”” ”'Power supply (power supply voltage), WD,, WD, /
, WD, , WD, /... Word driver. 'i, Dz: Anonymous itching D, ρ2

Claims (2)

[Claims] (1) In a semiconductor memory device in which information is written by flowing a current from a write terminal to destroy a junction, it is possible to include a suppressing voltage application circuit that applies a voltage generated at the write terminal during writing to an unselected word line. Characteristic semiconductor memory device. (2) The semiconductor memory device according to claim (1), wherein the suppression voltage application circuit has a thyristor structure, and is comprised of a circuit that operates during writing and does not operate during reading.