JPS61150182A - Input circuit of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an operating power source current approximate to DC by adding a feedback inverter for positively feeding back a part of an output to an inverter of an input circuit and a p type or an n type MOSFET to a previous stage of the output. CONSTITUTION:When a circuit threshold voltage of an input inverter 3 (INV3) is smaller than an electric potential V (=VDD-voltage of MOSFET 2) of a circuit point 5 and smaller than a VIH of a TTL input level, an electric potential of an output terminal 6 of the INV 3 is lowered to a ground level. Further, since this potential is inputted to a gate of a feedback inverter 4 (INV 4), when the potential of the circuit point 5 is raised to go above V, the MOSFET 2 is turned off, thereby the circuit point 5 is raised to VDD. Accordingly, a p type MOSFET 7 of the INV 3 is completely turned off and a penetrating electric current through the INV 3 and the INV 4 does not exist. As a result, also in the case of inputting the signal VIH by the TTL input level, the penetrating electric current opproximate to DC of the INV 3 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to an input circuit used in a semiconductor device such as a semiconductor memory.

2. Description of the Related Art Conventional input circuits for semiconductor memories of this type are generally so-called TTL compatible, in which input signals can be at TTL input level. Therefore, the third factor, an inverter as shown in FIG. 4, has been used as an input circuit for transmitting external signals to internal circuits.

FIGS. 3 and 4 are circuit diagrams of a CtMOS inverter, which is an example of a conventional semiconductor memory input circuit.

p-type MOS 57 system fi ”e P2r P5
Each input circuit is constituted by transistors N1, N2, and Ns.

Problems to be Solved by the Invention However, in such conventional input circuits, when the input signal from the outside is at the CMO8 level, there is no through current flowing from the power supply to the ground (GND). When a signal is input from the digital level section, there is a DC-like through current, so there is a problem in that the value of the so-called stipei current when a chip is not selected increases when a TTL input is made.

Figure 6 shows an example of the input circuit of a CkOS inverter.
The figure shows changes in the value of the DC through current with respect to the input signal level of the inverter. To explain using these figures, in Fig. 6, the input signal is set to 'H' (input When inputting to C8), when comparing the values of the DC through current at the CMO8 power level 0MO8 (VIH) and the TTL input power level TL (VIH), it is clear from the 64th graph. ,TTL
It can be seen that the nc-like through current increases when (VIH) is input. This is the reason why it is difficult to reduce the current during standby mode of the memory.

Therefore, the present invention makes it possible to reduce the DC-like through current when inputting a TTL input voltage level part signal during the standby mode of the memory.

Comparative means for solving the problems and technical means of the present invention for solving the above problems include at least one inverter in an input circuit for transmitting an external signal to an internal circuit, and a part of the output of the inverter as input. It includes an additional inverter to apply positive feedback, and an n- or p-type MOS transistor is arranged and connected in the preceding stage.

Effect With this configuration, for example, when the memory is in standby mode, if a five-CMO level signal is applied, it is almost the same as before (DC-like through current does not flow, and the input signal at TTI and input level is If the voltage is not applied, positive feedback is applied by the additional inverter, and T instantaneously increases.
TL entered Kashika level MO 8 people went to Kashika level,
When the level exceeds a certain level, the MOS transistor in the previous stage is turned off (OFF), and the DC-like through current of the reinverter can be brought to a state in which almost no DC through current flows, which eventually reaches the CMO5 input chip squid level.

Embodiment Hereinafter, an embodiment of the present invention will be explained together with FIGS. 1 and 2. FIG. 1 shows an input circuit of a semiconductor device according to an embodiment of the present invention. An external input signal is input to input point 1, and is applied to either the source or drain of N-type MOS transistor 2, whose gate is always given the 'IDD level, and then to input inverter 3. A part of the output of the 0-input inverter 3 is input to the feedback inverter 4, and the output of the feedback inverter 4 is connected to the input inverter 3 to form an input circuit.

Next, we will explain the operation of the MOS transistor 20 connected to the source or drain to which the above input signal is applied.
When the MOS transistor 2 starts to turn on, the potential at the circuit point 6 becomes lower than VDD by the threshold voltage vThn of the MOS transistor 2 (Vac - vThn). The potential at this circuit point 6 is input to the input inverter 3. Here, the circuit threshold voltage of the inverter 3 is (smaller than Vcc VThρ and TTL input voltage level I)! (H” level), the potential at the output terminal 6 of this inverter falls to the ground level.Furthermore, this potential is applied to the feedback inverter 4.
The voltage at the circuit point 6, which is input to the gate of
rises to. Therefore, the p-type MOS transistor 7Fi of the input inverter 3 is completely turned off, and the through current of the inverter and feedback inverter 4 no longer exists. Therefore, the value of the threshold voltage vThn of the N-type MO3) transistor 2 is selected as appropriate, and the drive capacity of the feedback inverter 4 is adjusted to the drive capacity of the input, taking into account the occurrence of competition between the input signal and the output of the feedback inverter 4. By making it about a fraction of
is transmitted correctly. Then, the input signal is positively fed back by the additional feedback inverter 10, and the input signal approaches the input signal level of the CMO5.

As a result, even when the input signal VII having the TTL input voltage level is input, the DC-like through current of the input inverter can be reduced. Further, since competition due to positive feedback of the feedback inverter signal ends instantaneously, no DC-like through current of the inverter flows, and the stein bar current does not increase.

Next, another embodiment of the present invention will be described with reference to FIG.

In the embodiment shown in FIG. 1, a case has been described in which the input signal to input terminal 1 (1C8) in the chip non-selected state, that is, in standby mode, is a TTL input level IH (H'' level) input signal. In the embodiment shown in FIG. 2, the input circuit is shown for the case where the input signal in the standby mode is at the TTL input level IL (L" level).

An input signal from the outside is input to an input circuit point 8, and is applied to either the source or the drain of a p-type MOS transistor 9 whose gate is always provided with a ground (GND) level.

The potential of the circuit point 10 connected to the source or drain of the transistor 9 becomes higher than the ground by the threshold voltage vTh (+V7h) at the start of turning on.

This potential at circuit point 10 is input to input inverter 11 . Similar to the configuration shown in the previous embodiment, a feedback inverter 12 is added to this, a part of the output of the input inverter 11 is input to the feedback inverter 12, and an output of the feedback inverter 12 is input to the input inverter 11. It is constructed by connecting as follows.

This operation is similar to the operation in the embodiment shown in FIG.
By approaching the ground level to the human power level, it becomes possible to significantly reduce the DC-like through current in the inverter.

However, it is a control signal (1C8) or (aS)
It has the effect of reducing the DC-like through current of the inverter, for example, for input circuits such as address pins other than when the level of the input signal is determined when the chip is not selected, or when the chip is selected. For example, it is necessary to connect in series with the N-type MOS transistor 2 shown in the embodiment of FIG. 1 to something similar to the p-type MOS transistor 9 used in the embodiment of FIG.

For example, in the embodiment shown in FIG. 1, the competition between the positive feedback by the feedback inverter and the input signal is made shorter and
In order to raise the O3 level, the conductance of the n-type MOS transistor 2 should be changed to the p-type MO3) transistor 13.
Furthermore, the relationship between the P-type MOS transistor 9 and the n-type MOS transistor 14 in the embodiment shown in FIG. 2 also needs to be designed in a similar manner.

Effects of the Invention The present invention includes a feedback inverter that positively feeds a part of its output to an inverter of an input circuit of a semiconductor device, and a p-type or n-type kO8) transistor added to the front stage of the output of the feedback inverter. With the input circuit configured by adding such a simple circuit, it is possible to convert the TTL input power level signal when the memory chip is not selected to the CMO5 input power level signal, and has the following effects. .

In other words, despite applying a TTL input level force signal, it is possible to instantaneously reach a level close to that of applying a CMO 8-level force signal, and it is possible to significantly reduce the standby current value to a level close to that of applying an input signal with an input level of 10MO3. Moreover, it can be applied as an input circuit to an input circuit for applying other input signals.

In addition, even when selecting a chip, it is possible to reduce the DC-like through current of the inverter of the input circuit.
It is possible to reduce the operating power supply current.

[Brief explanation of the drawing]

FIGS. 1 and 2 show the first embodiment of the present invention. A circuit diagram showing an input circuit of a semiconductor memory in the second embodiment, and FIG. 3 is a continuous current characteristic diagram showing an input circuit of a conventional semiconductor memory. 2.9...MO8 type transistor, 3,11.
...Input inverter, 4,12...Feedback inverter. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] An input circuit of a memory that receives a chip selection signal, is non-selected, and has an internal data retention function, includes at least one inverter that transmits an external signal to the internal circuit, and a part of the output of the inverter that is inputted and the output is transmitted to the input circuit. An additional inverter is input to the input terminal of the inverter to apply positive feedback, and an n- or p-type MO
An input circuit for a semiconductor device, characterized in that an S transistor is arranged and connected to the source or drain of the transistor.