JPS61149475A - Manufacture of high purity insulator target - Google Patents

Manufacture of high purity insulator target

Info

Publication number
JPS61149475A
JPS61149475A JP27802384A JP27802384A JPS61149475A JP S61149475 A JPS61149475 A JP S61149475A JP 27802384 A JP27802384 A JP 27802384A JP 27802384 A JP27802384 A JP 27802384A JP S61149475 A JPS61149475 A JP S61149475A
Authority
JP
Japan
Prior art keywords
high purity
target
purity
metallic
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27802384A
Other languages
Japanese (ja)
Inventor
Toshiyuki Shimizu
俊行 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27802384A priority Critical patent/JPS61149475A/en
Publication of JPS61149475A publication Critical patent/JPS61149475A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

PURPOSE:To manufacture a high purity insulator target for forming a high quality insulating thin film having a high dielectric constant by oxidizing or nitriding the surface layer of a high purity metallic target in an atmosphere of a high purity oxidizing or nitriding gas. CONSTITUTION:High purity metallic Ta 102 is fixed on a fixing Ta jig 103 in a quartz reaction tube 101 with Ta screws 104, and a metallic Ta plate 105 is placed in the tube 101 as a counter electrode. High purity gaseous O2 is introduced into the tube 101 from a gas introducing inlet 106 to fill the tube 101 with an atmosphere of high purity gaseous O2 under about 0.1-5Torr pressure. The jig 103 and the Ta plate 105 are connected to a high frequency power source 107, and plasma is generated between the metallic Ta 102 and the Ta plate 105 to oxidize the surface of the metallic Ta 102. By this oxidation a high purity Ta2O5 film 108 is formed on the surface of the metallic Ta 102, giving a high purity insulator target.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高純度絶縁体ターゲットの製作方法に関し、特
にスパッタリングにより高純度絶縁膜を形成するための
高純度絶縁体ターゲットの製作方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a high-purity insulator target, and particularly to a method for manufacturing a high-purity insulator target for forming a high-purity insulating film by sputtering.

〔従来の技術〕[Conventional technology]

半導体特にシリコン半導体上に形成する集積回路は高集
積化、大容量化の方向を辿り、メモリ素子の様な集積回
路ではメそり容量が256にビットから1Mビット又は
それ以上へと増大して来ている。この様な素子の大容量
化の中にあっては、歩留りやコストの点で極力チップサ
イズの縮小が行なわれねばならず、そのために高集積化
しfすい回路方式の検討9種々の微細加工技術、新材料
を用いる技術の開発が進められている0現在、ダイナミ
ックBλMの様なICメモリに於いては情報蓄積部(以
下セルと称す)を1個のトランジスタと1個の情報蓄積
容量部で構成するのが最も小屋化に適またものと考えら
れているが、該方式での情報蓄積方式では半導体ペレッ
トの大部分を占めるのは前記情報蓄積容量部でおる0こ
の理由から該方式によるダイナミックRAMの大容量化
に依るチップサイズの増大を抑えるためには情報蓄積容
量部の縮小が最も有効な手段となる0しかしこの情報蓄
積容量部容量は放射線によるメモリー内容消失効果を防
ぐために50fF程度以上確保しなければならない。然
るに現在用いられている技術をそのまま1M〜4Mピッ
)RAMに適用する場合、情報蓄積容量部面積を5μm
2としてシリコン基板を酸化したSin、膜を用いると
30〜401の膜厚となることが試算され、この膜厚で
はトンネル電流が流れてしまうため5i01膜は情報蓄
積容量部には使用出来なくなる。
Integrated circuits formed on semiconductors, especially silicon semiconductors, are trending toward higher integration and larger capacity, and the memory capacity of integrated circuits such as memory devices has increased from 256 bits to 1M bits or more. ing. In order to increase the capacity of such devices, it is necessary to reduce the chip size as much as possible from the viewpoint of yield and cost, and for this purpose, we are considering circuit systems that are easy to achieve high integration.9Various microfabrication techniques Currently, the development of technology using new materials is progressing, and in IC memories such as dynamic BλM, the information storage section (hereinafter referred to as a cell) is composed of one transistor and one information storage capacitor section. However, in the information storage method using this method, it is the information storage capacity section that occupies most of the semiconductor pellet.For this reason, the dynamic In order to suppress the increase in chip size due to the increase in the capacity of RAM, the most effective means is to reduce the information storage capacity. However, the capacity of this information storage capacity should be approximately 50 fF or more to prevent the effect of memory content loss due to radiation. must be secured. However, if the currently used technology is applied to a 1M to 4M bit RAM, the area of the information storage capacity should be reduced to 5μm.
It is estimated that if a Si film obtained by oxidizing a silicon substrate is used as No. 2, the film thickness will be 30 to 40 mm, and with this film thickness, a tunnel current will flow, so the 5i01 film cannot be used for the information storage capacitor section.

これを打開するために溝堀り凰容量形成技術。To overcome this problem, Mizohori Capacity Formation Technology is used.

積層型容量形成技術、高誘電率材料を用いた容量形成技
術、及びこれらを組み合わせた技術等が従来技術に代わ
るものとして有力視されている。特に高誘電率材料を用
いた情報蓄積容量部形成技術は更に高密度化する集積回
路に於いても適用出来るため重要な技術である。しかし
高誘電薄膜はシリコン以外の元素の膜をシリコン基板上
に形成するなめシリコン基板を熱酸化した8 i 0x
 gXよりもリーク電流や耐圧の点で劣ることが問題で
るる。
Laminated capacitor formation technology, capacitance formation technology using high dielectric constant materials, and technologies that combine these are considered to be promising alternatives to conventional technology. In particular, the technology for forming an information storage capacitor using a high dielectric constant material is an important technology because it can be applied to integrated circuits that are becoming more densely packed. However, high dielectric thin films are made by thermally oxidizing a silicon substrate to form a film of an element other than silicon on a silicon substrate.
The problem is that it is inferior to gX in terms of leakage current and breakdown voltage.

これを解決するために膜の被着法の検討や膜質を向上さ
せるために、膜の組成の制御が必要となりこのために高
純度の膜を被着させる技術が必要となる。
To solve this problem, it is necessary to study the film deposition method and to control the composition of the film in order to improve the film quality, and for this purpose, a technique for depositing a highly pure film is required.

膜形成方式としては大別してスパッタ法やCVD法があ
る。CVD法は原料ガスに化合物を用いるため、被着さ
せる膜の成分以外の異元素が入夕純度が上がらない。前
記異元素を含まない原料を用い九場合にもこの原料の蒸
気圧が低い、安全性に問題がちる等の問題がらり、実用
に不適又は実用の際には装置が大がかりKなる問題がめ
った。
Film forming methods can be roughly divided into sputtering methods and CVD methods. Since the CVD method uses a compound as a raw material gas, the purity of foreign elements other than the components of the film to be deposited does not increase. Even when using a raw material that does not contain the above-mentioned foreign elements, there are problems such as low vapor pressure of the raw material, safety problems, etc., and problems such as making it unsuitable for practical use or requiring a large-scale equipment for practical use are common.

スパッタ法はターゲットが出来れば大がかりな装置なし
に膜を被着できるのでCVD法に比べ装置が簡単で済む
メリットがある。スパッタ法で絶縁薄膜を形成するには
高純度金属ターゲットをスパッタリングし、基板上に被
着させ、この金属薄膜を酸化して絶縁膜形成を行なう方
法と、絶縁物ターゲットをRFスパッタし、基板上に絶
縁膜を被着させる方法がある〇 〔発明が解決しようとする問題点〕 前者の場合は熱酸化の際に体積膨張や粒成長のために膜
にクラックが入夕、これが電流通路となりリーク電流の
増加を来たすという問題が6った。
The sputtering method has the advantage of requiring simpler equipment than the CVD method, since a film can be deposited without a large-scale device once a target is prepared. To form an insulating thin film by sputtering, there are two methods: sputtering a high-purity metal target, depositing it on a substrate, and oxidizing this metal thin film to form an insulating film; In the former case, cracks appear in the film due to volume expansion and grain growth during thermal oxidation, which become current paths and cause leakage. There was a problem that the current increased.

後者は密度の比較的高い、リーク電流の少ない膜が形成
できるため有効な膜被着法であるが、ここで用いるター
ゲットは従来絶縁物にバインダーと呼ばれる焼結剤を添
加し、成製、焼結、加工して用いており、このバインダ
ーのためにターゲットの純度を99.91以上に上げる
ことが困雄であフ基板上に形成する膜の純度が上がらな
かった。又純度が上がらないために、不純物添加した時
の組成の再現性が乏しく電気的特性の再現性も乏しかっ
た。この様に膜の純度を向上させるためにターゲットの
純度を向上させることが必要であるが、これを解決する
有効な手段は未だ見つかっていない0 本発明は上記のターゲット純度が上がらない欠点を解消
し集積回路の高密度化を計る上で不可欠な高誘電絶縁薄
膜形成のための高純度絶縁膜ターゲットを提供すること
を目的とする。
The latter is an effective film deposition method because it can form a film with relatively high density and low leakage current, but the target used here is conventionally formed and sintered by adding a sintering agent called a binder to an insulator. However, because of the binder, it was difficult to increase the purity of the target to 99.91 or higher, and the purity of the film formed on the substrate could not be increased. Furthermore, since the purity was not increased, the reproducibility of the composition when impurities were added was poor, and the reproducibility of the electrical characteristics was also poor. In order to improve the purity of the film, it is necessary to improve the purity of the target, but an effective means to solve this problem has not yet been found.The present invention solves the above-mentioned drawback that target purity does not increase. The purpose of this research is to provide a high-purity insulating film target for forming a high dielectric insulating thin film, which is essential for increasing the density of integrated circuits.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の高純度絶縁体ターゲットの製作方法は、スパッ
タ法で絶縁膜を形成する際に用^る絶縁体ターゲットの
製作方法において、スパッタ被着する絶縁薄膜の主成分
である高純度金属のターゲットを準備する工程と、該高
純度金属のターゲットを高純度の酸化ガス或は窒化ガス
雰囲気中で酸化或は窒化して該高純度金属の表面に高純
度酸化物層或は窒化物層を形成する工程とを含んで構成
される。
The method for manufacturing a high-purity insulator target of the present invention is a method for manufacturing an insulator target used when forming an insulating film by sputtering. and oxidizing or nitriding the high-purity metal target in a high-purity oxidizing gas or nitriding gas atmosphere to form a high-purity oxide layer or nitride layer on the surface of the high-purity metal. The process includes the steps of:

〔実施例〕〔Example〕

次に本発明の実施例について、図面を参照して説明する
。本実施例では金属Taを酸化し、表面OTax Os
 t”スパッタリングしてシリコン基板上にTa、0.
を形成する例を取シ上げるが、絶縁膜はZrO,等信の
絶縁材料にも適用でき、基板はGaAs等の化合物半導
体基板にも同様く適用できる0 第1図は本発明の一実施例の絶縁体ターゲットを実現す
る念めの酸化装置の概略図である。反応石英管101内
に高純度金属Ta102をTa製固定治具103にTa
製ビス104にて固定する。
Next, embodiments of the present invention will be described with reference to the drawings. In this example, metal Ta is oxidized to form a surface OTax Os
t'' sputtering to deposit Ta,0.
Although we will take an example in which the insulating film is formed of an insulating material such as ZrO, the insulating film can also be applied to an insulating material such as ZrO, and the substrate can be similarly applied to a compound semiconductor substrate such as GaAs. FIG. 2 is a schematic diagram of an oxidation device for realizing an insulator target. A high-purity metal Ta102 is placed in a reaction quartz tube 101 in a Ta fixing jig 103.
Fix with manufactured screws 104.

対向電極として金属Ta板105を設け、反応石英管1
01内を減圧にし、ガス導入口106よp高純度0.ガ
スを導入し、01〜5 Torrの圧力にする。次KT
a電極102,105間に高周波電源107を接続し、
13.56■hの高周波をかけてプラズマを発生させ高
純度金属Ta 102の表面を酸化し、ターゲットを得
る。高純度金属Taの酸化は熱酸化を用いても良い。こ
の場合は500℃以上の温度でO,ガスを用いて酸化す
れば良い。
A metal Ta plate 105 is provided as a counter electrode, and the reaction quartz tube 1
01 is reduced in pressure, and the gas inlet 106 is heated to high purity 0. Introduce gas and bring the pressure to 01-5 Torr. Next KT
A high frequency power source 107 is connected between the a electrodes 102 and 105,
Plasma is generated by applying a high frequency of 13.56 h to oxidize the surface of the high purity metal Ta 102 to obtain a target. The high purity metal Ta may be oxidized by thermal oxidation. In this case, oxidation may be performed using O or gas at a temperature of 500° C. or higher.

第2図に上記Ta102を酸化して得た絶縁膜ターゲッ
トの構造を示す。’ratoz上に高純度Ta、O,膜
108を有する構造となる。)Ta10゜108は十分
厚く成長させることができるが、少なくとも1000Å
以上あれば良い。
FIG. 2 shows the structure of an insulating film target obtained by oxidizing Ta102. The structure has high-purity Ta, O, and a film 108 on the 'ratoz. ) Ta10°108 can be grown thick enough, but at least 1000 Å
More than that is fine.

このターゲットをスパッタ装置のターゲット装置治具に
取り付は后ガスを用いてRFスパッタリングを行なうこ
とによp1対向するシリコン基板上に高純度の’ra!
0. [を形成する。形成した膜の純度は99.99−
以上となる。この膜を低!当アニールすることによ!1
)(600℃以下)従来リーク電流が10−’A/m2
程Ifあったものがs O−1!、A/−2と改善され
た。金属ターゲット102表面のTa、 o、膜10g
が減少して来た場合にはターゲット102を取り出して
可変熱酸化するか、もしくはターゲット102をスパッ
タ装置にa4したtまプラズマ酸化する等の方法で金属
ターゲット102表面にra*0* 108を成長させ
ターゲットを再生すれば良い。
After attaching this target to the target device jig of the sputtering device, high-purity 'ra!
0. [to form. The purity of the formed film is 99.99-
That's all. Low this membrane! Let's do the annealing! 1
) (below 600℃) Conventional leakage current is 10-'A/m2
The one that was about s O-1! , improved to A/-2. 10 g of Ta, O, film on the surface of the metal target 102
When the metal target 102 decreases, ra*0* 108 is grown on the surface of the metal target 102 by taking out the target 102 and subjecting it to variable thermal oxidation, or by placing the target 102 in a sputtering device and subjecting it to plasma oxidation. All you have to do is play the target.

本方法によフリーク電流の少ない高純度高誘電*’ra
tow薄膜が形成できる。
This method provides high-purity, high-dielectric properties with low leakage current *'ra
A tow thin film can be formed.

本発明によるターゲットを用いて不純物を添加する際に
は、反応性スパッタリング法を用いれは実現できる。例
えば炭素を入れる場合にはCO3とO2をスパッタガス
に混入させれば良い。又窒素を入れる場合にはN、とO
,ガスを用いれば良い。
When adding impurities using the target according to the present invention, a reactive sputtering method can be used. For example, when carbon is added, CO3 and O2 may be mixed into the sputtering gas. Also, when adding nitrogen, N, and O
, gas can be used.

又不純物の浸度は添加するCO,、N、分圧を変化させ
ることにより可能となる。
Furthermore, the degree of impurity penetration can be changed by changing the added CO, N, and partial pressures.

この方法により膜組成を制御し、特性の制御された膜の
形成が可能どなる。
This method makes it possible to control the film composition and form a film with controlled properties.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、集積回路の高密
度化を計る上で不可欠な高誘電絶縁薄膜形成の念めの高
純度絶縁膜ターゲットが得られ、その結果膜組成の制御
が容易となり、従来の金属スパッタした後熱酸化した膜
よりも密It″が高く、クラックもすくなく、純度の高
い膜が形成できるため、従来よりもリーク電流の少ない
良質の膜が形成可能となる。
As explained above, according to the present invention, a high-purity insulating film target for forming a high dielectric insulating thin film, which is essential for increasing the density of integrated circuits, can be obtained, and as a result, the film composition can be easily controlled. As a result, it is possible to form a film with a higher density It'', fewer cracks, and higher purity than the conventional film formed by thermally oxidizing after metal sputtering, making it possible to form a high-quality film with less leakage current than before.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の絶縁体ターゲットを実現す
る丸めの酸化装置の概略図、第2図は本発明によシ得ら
れ念高純度絶縁体ターゲットの構造説明図である。 101・・・・・・反応石英管、1o2・・・・・・高
純度金属Ta%103・・・・・・Tag固定治具、1
04・・・・・・Ta製ビス、1o5・・・・・・金J
iTa対向電櫃、 1o6・・・・・・ガス導入口、1
o7・・・・・・高周波電源、108・・・・・・高純
度ThOwf’ii。 代理人 弁理士 内 原  晋t’ :’8$及島4失
管    高純度金属Tゐ 高純度TttxOr榎
FIG. 1 is a schematic diagram of a round oxidation apparatus for realizing an insulator target according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the structure of an extremely high purity insulator target obtained by the present invention. 101... Reactive quartz tube, 1o2... High purity metal Ta% 103... Tag fixing jig, 1
04...Ta screw, 1o5...Gold J
iTa opposing electrical box, 1o6...Gas inlet, 1
o7... High frequency power supply, 108... High purity ThOf'ii. Agent Patent Attorney Susumu Uchihara: '8$ and Island 4 Lost High Purity Metal T2 High Purity TttxOr Enoki

Claims (1)

【特許請求の範囲】[Claims] スパッタ法で絶縁膜を形成する際に用いる絶縁体ターゲ
ットの製作方法において、スパッタ被着する絶縁薄膜の
主成分である高純度金属のターゲットを準備する工程と
、該高純度金属のターゲットを高純度の酸化ガス或は窒
化ガス雰囲気中で酸化或は窒化して該高純度金属表面に
高純度酸化物層或は窒化物層を形成する工程とを含むこ
とを特徴とする高純度絶縁体ターゲットの製作方法。
A method for manufacturing an insulator target used when forming an insulating film by sputtering includes a step of preparing a high-purity metal target, which is the main component of the insulating thin film to be sputtered, and oxidizing or nitriding in an oxidizing gas or nitriding gas atmosphere to form a high-purity oxide layer or nitride layer on the high-purity metal surface. Production method.
JP27802384A 1984-12-25 1984-12-25 Manufacture of high purity insulator target Pending JPS61149475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27802384A JPS61149475A (en) 1984-12-25 1984-12-25 Manufacture of high purity insulator target

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27802384A JPS61149475A (en) 1984-12-25 1984-12-25 Manufacture of high purity insulator target

Publications (1)

Publication Number Publication Date
JPS61149475A true JPS61149475A (en) 1986-07-08

Family

ID=17591568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27802384A Pending JPS61149475A (en) 1984-12-25 1984-12-25 Manufacture of high purity insulator target

Country Status (1)

Country Link
JP (1) JPS61149475A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290693A (en) * 1988-09-28 1990-03-30 Shimada Phys & Chem Ind Co Ltd Thin film electronic component and manufacture thereof
WO2012164797A1 (en) * 2011-06-03 2012-12-06 パナソニック株式会社 Thin film formation method, thin film formation device, production method for display panel, production method for display device, and production method for light-emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290693A (en) * 1988-09-28 1990-03-30 Shimada Phys & Chem Ind Co Ltd Thin film electronic component and manufacture thereof
WO2012164797A1 (en) * 2011-06-03 2012-12-06 パナソニック株式会社 Thin film formation method, thin film formation device, production method for display panel, production method for display device, and production method for light-emitting device

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