JPS61148535A - Function type/logical type language processor - Google Patents

Abstract

PURPOSE:To execute easily development and debug, and also to cope flexibly with a function change and extension by placing an exclusive processor for scheduling an trap processing, and providing a hardware stack by which a register, etc. are saved automatically when a trap is generated, in a language processing processor. CONSTITUTION:A language processing processor 6 is constituted so that a micro-instruction prepared in advance in a control memory 17 is executed by an arithmetic unit 18 by utilizing a register 19, and an Lisp language is processed. A hardware stack 16 is used for transfer, etc. of information of an Lisp function. On the language processing processor 6, especially, a system use hardware stack 15 is provided. The system use hardware stack 15 is a memory circuit in which internal state information in the language processing processor 6 of the contents, etc. of various registers is stored automatically, in case a trap or an interruption request for discontinuing an execution of the language processing processor 6 is generated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a functional/logical language processing device, and particularly to a functional/logical language processing device.

A language processing processor is a dedicated processing device such as a so-called Lisp machine or a Prolog machine, and processes a functional language or a logical language.

The present invention relates to a functional/logical language processing device that uses a general-purpose sequential processor to process scheduling, trap processing, garbage collection, etc. for a process given as a language processing unit.

[Conventional technology and problems]

Research on artificial intelligence has recently become active, and functional languages such as Li5p and logical languages such as Prolog are attracting attention as programming languages. Various specialized processing devices have been developed to efficiently process these languages.

FIG. 6 shows a system example of a conventional bank-end type Li5p machine.

In FIG. 6, reference numeral 1 denotes a host processing unit made of a general-purpose computer, 2 a console display, 3 an external storage device such as a magnetic disk device, and 4 a channel interface device such as a channel coupling device.

5' represents a main memory for language processing, and 6' represents a processor for language processing.

Operator interaction with the system is via the console display 2 of the host processor 1. For example, when a request is made to execute a program written in Lisp prepared in advance in the external storage device 3, the host processing device 1, via the channel interface device 4,
The program is transferred to the main memory 5' and the language processing processor 6' is requested to execute it.

The language processing processor 6' interprets and executes the Li5p language under microprogram control, and sends the processing results through the channel interface device 4.

Notify host processing device l.

The control operations of the language processing processor 6' are defined by Li5p functions and microprograms.
When attempting to process multiple processing requests from the host processing device 1, an operating system is required to schedule each processing request. Also, main memory 5
In connection with ', it is necessary to perform various types of trap processing and processing such as so-called garbage collection to collect unnecessary areas on the main memory 5'.

゛ Conventionally, the language processing processor 6' has been configured to perform processing request scheduling, various trap processing, etc. using its instruction system, so the operating system must be written using Lisp functions or microprograms. Not.

There were the following problems.

■ During scheduling and trap processing, garbage
When collection occurs, control information may be lost, so Li
Unable to use sp function.

Available functions are limited.

■ The part written by microprogram.

Debugging is difficult, and when a bug occurs, it is difficult to detect and correct the error location.

■ It is particularly difficult to take measures against garbage collection, and when extending the functionality of the operating system, the instruction system that can be executed by the language processing processor 6' is not included in the operating system description, which reduces development man-hours. It costs a lot.

[Means for solving problems]

The present invention aims to solve the above problems by providing a processor dedicated to scheduling and trap processing.

Processing that corresponds to the functions of an operating system, which was traditionally carried out by language processing processors.

In addition to reducing the processing load on the language processing processor by running it on the newly installed processor, the language processing processor also provides a hardware stack in which registers and the like are automatically saved when a trap occurs. This prevents processing conflicts from occurring due to trap processing and the like being processed outside the language processing processor. In other words, the functional/logical language processing device of the present invention has the following features:
In a functional/logical language processing device that processes a functional language or a logical language capable of list processing, the language processing unit is managed as a process, execution is scheduled for the process, and trap processing including garbage collection is executed. a language processing processor that executes processing using a functional language or a logical language regarding each of the above processes under microprogram control; and an interface between the process control processor and the language processing processor regarding process control. It also has a memory for use.

The language processing processor includes a system hardware stack in which internal state information is saved when a trap occurs, and the process control processor transmits the process to be processed to the language processing processor via the interface memory. It is characterized by being configured to notify environmental information. An embodiment will be described below with reference to one drawing.

〔Example〕

FIG. 1 is a system configuration diagram of an embodiment of the present invention, FIG. 2 is an internal processing configuration diagram of the process control processor shown in FIG. 1,
FIG. 3 is an explanatory diagram of the system hardware stack, FIG. 4 is an explanatory diagram of control when a trap occurs, and FIG. 5 is an explanatory diagram of processing when an interrupt occurs.

In FIG. 1, numerals 1 to 4 correspond to FIG. 6.

5 is a main memory, 6 is a language processing processor, 7 is a process control processor that executes process scheduling and trap processing, etc., 8 is a local memory, 9 is a queue terminal, and 10-1 and 10-2 are process management tables. , 13 is high-speed memory, 14 is high-speed memory 13
15 is a system hardware stack, 16 is a hardware stack used by the language processing processor 6 for language processing, and 17 is a control memory in which a microprogram is stored (C3
), 18 represents an arithmetic unit, and 19 represents various registers in the language processing processor including a register file.

The software interface with the host processing device 1 may be considered to be similar to the conventional example shown in FIG.

That is, the conventional software in the host processing device 1 can be used as is. The main memory 5 is managed by virtual memory, and each Li5p language processing request unit from the host processing device 1 is associated with a resource allocation unit called a process.
area is allocated.

Hardware stack 16 of language processing processor 6.
Control memory 17. Arithmetic unit 18 and various registers 1
9 can be considered to be similar to a conventional Lisp machine. That is, the language processing processor 6 executes microinstructions prepared in advance in the control memory 17 by the arithmetic unit 18 using the register 19, and
It is designed to process p language. The hardware stack 16 is.

L　Used for information inheritance of the isp function.

In the case of the present invention, the language processing processor 6 includes:

In particular, a system hardware stack 15 is provided. The system hardware stack 15 is.

This is a memory circuit in which internal state information in the language processing processor 6, such as the contents of various registers 19, is automatically stored when a trap or interrupt request that interrupts the execution of the language processing processor 6 occurs. The system hardware stack 15 is.

For example, as shown in FIG. 3, it consists of a pointer section 21 and a register storage section 22, and the register storage section 22 is divided into blocks corresponding to each process.

The pointer section 21 is accessed by a process number PNO that uniquely identifies a process, and points to an area of the register storage section 22 in which register information and the like of the process is stored.

The process control processor 7 is a device that fetches and executes instructions prepared in advance in the local memory 8, and is realized by, for example, a minicomputer, a microcomputer, or the like. The process control processor 7 exclusively processes processing corresponding to an operating system, which has conventionally been processed by the language processing processor 6. That is.

Process control based on requests from the host processing device 1,
Trap processing and the like that occur with virtual memory management of the main memory 5 are executed by sequentially processing nine machine language instructions. Information regarding each process is provided in the process management table 10-
1. . . . is managed, process management table 10-1. ...depends on the order of processing requests and waiting status.
It is queued from the queue terminal 9 and managed.

The high-speed memory 13 is a cache memory for an interface between the process control processor 7 and the language processing processor 6. For example, when switching the process processed by the language processing processor 6, the register information saved in the system hardware stack 15 is saved in the high-speed memory 13, and the register information etc. of the process to be newly executed is transferred to the high-speed memory 13. The data is transferred from the process control processor 7 to the language processing processor 6 via the memory 13. The usage flag 14 is a flag for notifying the process control processor 7 whether the contents of the system hardware stack 15 have been stored in the high-speed memory 13 or not.

The internal processing configuration of the process control processor 7 is as follows.

For example, it is as shown in FIG. Interrupt analysis section 3
0 transfers control when a trap or normal interrupt occurs, analyzes the cause of the interrupt, and activates various processing units corresponding to the 2 interrupt.

If the cause of activation of the interrupt analysis unit 30 is 2, for example, a memory-related trap, the trap processing unit 31 is called;

Perform the processing requested by the trap. Also.

In the case of garbage collection, the garbage collector 32 is activated, and the garbage collector 32 executes processing to collect an area on the main memory 5 that is no longer needed. The processing of the trap processing unit 31 and the garbage collector 32 does not need to be written using microinstructions or Li5p functions, and can be written using a language used by ordinary general-purpose computers, so it can be created relatively easily. can.

When the cause of activation of the interrupt analysis unit 30 is inter-process communication, a processing request from the host processing device 1, etc., the scheduler 33 is activated. The scheduler 33 depends on the specific content of the processing request.

Process control is performed as follows. When the request is a process establishment request from the host processing device 1.

The LOGON processing unit 37 is called, a process management table is created, and a new process is generated. In addition, if it is a process termination request, the TSSEND processing unit 3
4 and executes the process to kill the process.

For example, when an input/output command completion cycle or a notification event to a process occurs, the PO3T processing unit 36 is called, the process is released from the waiting state, and the process is requeued to the executable state.

On the other hand, if a process issues a request to wait for an event to occur,
The WAIT processing unit 35 sets the process to a waiting state.

Once you are ready to run other processes,
Control is transferred to the sleeve processing section 38.

The sleeve processing unit 38 refers to the process management table, selects an executable process, and sets the main memory environment setting unit 39.
Transfer control to The main memory environment setting unit 39 executes processing to prepare the virtual memory environment on the main memory 5 regarding one selected process. Next, the timer-related control unit 40 switches time information related to the processing time and the like of the process. and.

The process switching unit 41 is activated. Process switching section 4
1 extracts register information etc. from the process management table of the newly executed process.

The contents are stored in the high-speed memory 13 and the process environment is set. Then, a processing request is issued to the language processing processor 6. As a result, a new process will be processed by the language processing processor 6.

Next, control when a trap occurs will be explained with reference to FIG.

(2) When a trap occurs, processing in the language processing processor 6 is interrupted, and register information, etc. currently being used by the language processing processor 6 is lost.

It is saved to the system hardware stack 15.

(2) At the same time, a trap request is transmitted to the process control processor 7, and the process control processor 7 executes processing corresponding to the trap request. The trap switching flag 5o is a flag indicating whether the trap is a normal trap or a trap that requests garbage collection. When this flag is ON, the garbage collector 32 executes garbage collection. Ru. Note that garbage collection is targeted at the area of the user process where the garbage collection request occurred.

During its execution, the language processing processor 6 can process other user processes by process switching.

(2) When the trap processing is completed, the process control processor 7 notifies the language processing processor 6 of the completion.

(2) When the language processing processor 6 receives the trap completion notification, it loads the register information etc. saved in the system hardware stack I5.

■ Then resume execution of the process in which the trap occurred. In addition, in the trap processing in the process control processor 7, if a swap-in/swap-out of a program, etc. on the main memory 5 occurs, the process is switched in the same way as in the case of interrupt processing, which will be described later.
Perform processing for other executable processes.

When an interrupt other than a trap occurs, control is performed as shown in FIG.

(2) The language processing processor 6 saves register information and the like in the high-speed memory 13 in response to one interrupt request. Note that while register information and the like are being saved to the high-speed memory 13, the use flag 14 is set to ON, and when the saving is completed, the use flag 14 is turned OFF.

■ At the same time, the process control processor 7.

The interrupt request is analyzed, and the scheduler 33 performs process scheduling and dispatch processing.

(2) When using the register information of the language processing processor 6 in dispatch processing, refer to the use flag 14 to check whether the save has been completed. If only it had ended.

The register information and the like are set in the process management table related to the interrupt.

■ Next, obtain register information, etc. of the process to be newly executed from the process management table.

Set in high-speed memory 13.

(2) Then, the language processing processor 6 is notified of the completion of scheduling by interrupt. The process control processor 7 then waits for a scheduling opportunity such as a secondary interrupt.

(2) When the language processing processor 6 receives the notification of completion of scheduling from the process control processor 7, it loads register information and the like related to the new process from the high speed memory 13.

(2) By setting the register information of the new process to zero in the language processing processor 6, the language processing processor 6 will thereafter execute the processing of the switched process.

In the above embodiment, as the language processing processor 6,
I explained what deals with the Li5p language.

It goes without saying that the process control processor 7 can similarly perform various trap processing and process scheduling processing for other processing devices dedicated to language processing, such as a so-called Prolog machine.

〔Effect of the invention〕

As described above, according to the present invention, trap processing and scheduling processing, which have conventionally been difficult with the instruction processing system of a language processing processor, can be realized using the instruction processing function of a normal computer. Therefore,
Development becomes easier, debugging becomes easier, and changes and expansions of functions can be dealt with flexibly. Furthermore, since the processing load on the language processing processor is reduced, processing performance is improved.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention, FIG. 2 is an internal processing configuration diagram of the process control processor shown in FIG. 1,
Figure 3 is an explanatory diagram of the system hardware stack, Figure 4 is a diagram to explain control when a tiger/knob occurs, Figure 5 is an explanatory diagram of processing when an interrupt occurs, and Figure 6 is a diagram of the conventional backup system. A system example of an end-type Li5p machine is shown. In the figure, 1 is a host processing unit, 2 is a console display, 3 is an external storage device, 4 is a channel interface device, 5 is a main memory, 6 is a language processing processor, and 7 is a process control processor. 8 is local memory, 9 is queue terminal, 1O-1
10-2 are process management tables. I3 represents a high speed memory, 14 represents a use flag, 15 represents a system hardware stack, 16 represents a hardware stack, 17 represents a control memory, 18 represents an arithmetic unit, and 19 represents a register. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori (1 other person) Figure 2

Claims (1)

[Claims] In a functional/logical language processing device that processes a functional language or a logical language capable of list processing, the language processing unit is managed as a process, execution is scheduled for the process, and trap processing including garbage collection is executed. a language processing processor that executes processing using a functional language or a logical language regarding each of the above processes under microprogram control; and an interface between the process control processor and the language processing processor regarding process control. The language processing processor also includes a system hardware stack in which internal state information is saved when a trap occurs, and the process control processor has a memory for language processing via the interface memory. A functional/logical language processing device, characterized in that it is configured to notify a processor of process environment information to be processed.