WO2023169289A1

WO2023169289A1 - Method and apparatus for switching execution status of process

Info

Publication number: WO2023169289A1
Application number: PCT/CN2023/079222
Authority: WO
Inventors: 童甜根; 郭寒军; 王克锋
Original assignee: 华为技术有限公司
Priority date: 2022-03-11
Filing date: 2023-03-02
Publication date: 2023-09-14
Also published as: CN116775234A

Abstract

A method and apparatus for switching the execution status of a process, for use in switching, when a master logic core and a slave logic core are decoupled, a process running in the slave logic core to the master logic core for running. In the present application, the method comprises: if a process running in a slave logical core satisfies a first condition, suspending running of the process in the slave logical core, and recording the suspension position of the process, wherein the suspension position is used for determining an execution position when running the process in the slave logic core next time, the first condition is used for indicating a target operation to be executed of the process, and the target operation can be executed when the execution status of the process is in a privileged mode of a master logic core; switching the execution status of the process from a user mode of the slave logic core to the privileged mode of the master logic core; and running the process in the master logic core for the process to execute the target operation.

Description

A method and device for switching execution state of a process

Cross-references to related applications

This application claims priority to the Chinese patent application submitted to the China Patent Office on March 11, 2022, with application number 202210238502.2 and the application title "A method and device for switching execution state of a process", the entire content of which is incorporated by reference in in this application.

Technical field

The present application relates to the field of processors, and in particular, to a method and device for switching execution states of a process.

Background technique

Modern computers are facing increasingly complex computing requirements. The central processing unit (CPU) of one architecture can no longer meet business needs. Many solutions will choose heterogeneous computing. The so-called heterogeneous refers to the combination of CPU, digital signal processing (DSP), graphics processing unit (GPU), application specific integrated circuit (ASIC), field programmable logic gate array (field Computing units with different process architectures, different instruction sets, and different functions such as programmable gate array (FPGA) are combined to form a hybrid computing system.

Taking the ARMv8-A architecture as an example, the CPU physical core includes the ARM64 logical core and the ARM32 logical core. The ARM64 logical core can execute one of the privilege levels EL0 to EL4, and the ARM32 logical core can execute the privilege level EL0, among which the privileges of EL0 The lowest level. When running an ARM32 process in the ARMv8-A architecture, the ARM32 process specifically runs in the ARM32 logical core. However, when the ARM32 process needs to perform high-privilege level operations (such as system calls), an exception needs to be triggered so that the ARM32 process The execution state is trapped from privilege level EL0 to privilege level EL1, thereby executing the high-privilege level operation in the ARM64 logic core. Subsequently, the execution status of the ARM32 process returns from privilege level EL1 to privilege level EL0 again, and execution continues in the ARM32 logical core.

In this method, the ARM64 logic core and the ARM32 logic core need to be tightly coupled. For example, the ARM64 logic core needs to add new registers and vector table entries to support the ARM32 logic core. The two logic cores cannot evolve independently.

Contents of the invention

This application provides a process execution state switching method and device, which are used to decouple two logical cores on the premise of flexibly switching the corresponding execution states of two logical cores, so that one of the logical cores can be independently evolved.

In the first aspect, this application provides a method for switching the execution state of a process, which is applied to a CPU. The CPU includes a physical core, and the physical core includes a master logical core and a slave logical core. The method includes: if running on the slave When the process of the logical core meets the first condition, the running process is suspended from the logical core, and the pause position of the process is recorded. The pause position can be used to determine the execution position when the process is run from the logical core next time, where the first condition is Instructs the process to perform the target operation, and the target operation can be executed when the execution state of the process is in the privileged state of the main logical core; switches the execution state of the process from the user mode of the slave logical core to the privileged state of the main logical core; in Processes run in the main logical core for the process to perform target operations.

In the above technical solution, when a process is run from a logical core and the process needs to perform a target operation, the process is run from the logical core Record the pause position of the process, which can be used to determine the execution position the next time the process is run in the slave logical core. In this way, the master logical core and the slave logical core do not need to share registers, and can flexibly switch the corresponding execution states of the two logical cores. Under the premise of decoupling the two logic cores, one of the logic cores can be evolved independently.

In one possible implementation, recording the pause position of the process includes writing the pause position information into the configuration space through the slave logical core, and the configuration space is used for information interaction between the master logical core and the slave logical core. By configuring the configuration space for information interaction between the slave logic core and the master logic core in the physical core, the master logic core and the slave logic core are decoupled, so that the master logic core and the slave logic core can develop independently. Under the premise of destroying the architectural semantics/instruction space corresponding to the main logical core, the independent evolution of the instruction set corresponding to the slave logical core can be achieved.

In a possible implementation, the method also includes: switching the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; reading the pause position information from the configuration space through the slave logical core; In the logical core, the process continues from the paused position. In this way, after the main logical core completes the target operation, the slave logical core can continue to be started to continue running the process. Since the slave logical core has previously recorded the pause position, the slave logical core can continue to run from the pause position, thereby realizing that the process can Switch between two logical cores and the process can run without interruption.

In a possible implementation, the first condition includes the process triggering a first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions; the execution status of the process is Switching from the user mode of the slave logical core to the privileged state of the main logical core includes: triggering the main logical core to run a process to switch the execution state of the process from the user mode of the slave logical core to the user mode of the main logical core; Determine the target privilege level corresponding to the first type of exception among multiple privilege levels of the privileged state; switch the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core.

In one possible implementation, before switching the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, the method further includes: obtaining the virtual memory address corresponding to the target privilege level; determining the virtual memory address of the target privilege level; The memory address is not mapped to the physical memory address.

In the above technical solution, the main logical core accesses the virtual memory address corresponding to the target privilege level. If it is determined that the virtual memory address does not establish a mapping relationship with the physical memory address, a page fault is triggered. The main logical core can process the process based on the triggered page fault. The execution state falls from the user state of the main logical core to the target privilege level of the privileged state of the main logical core. In this way, by constructing a special exception (ie, page fault), the execution state of the process is dropped from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, thereby reducing the complexity of the execution of the process falling into the privileged state.

In a possible implementation, the first condition includes the process receiving an interrupt, or the process triggering a RAS exception. Since interrupts or RAS exceptions are asynchronous events and need to be processed quickly, when the process running on the slave logical core receives an interrupt or triggers a RAS exception, the process can be processed through the hardware unit (or hardware part) in the CPU physical core. The execution state falls from the user state of the slave logical core to the target privilege level of the privileged state of the main logical core.

In a possible implementation, the method also includes: starting the process in the main logical core; if the instruction set of the process belongs to the instruction set running from the slave logical core, recording the starting position of the process and triggering the slave logical core to enter the running state. ;In the slave logical core, run the process from the starting position. In the above technical solution, some processes (such as mySql process, graph calculation process or encryption and decryption operators) need to run in the slave logical core. When starting these processes in the main logical core, it can be determined that these processes need to run in the slave logical core. In the slave logical core, the starting position of the process is recorded through the main logical core, and the slave logical core is triggered to enter the running state, so that the slave logical core reads the starting position and runs the process at the starting position.

In a possible implementation, the method further includes: releasing the hardware resources of the physical core occupied by the main logical core when running the process; where the hardware resources include memory resources and/or input and output resources. In this way, the released hardware resources can be reused to run other processes, which helps to fully utilize the hardware resources.

In a possible implementation, the method also includes: recording one or more of the following information from the logical core: the reason why the running process is suspended on the logical core, the execution parameters corresponding to the target operation, and when the running process is suspended. Environment information, or privilege level information; where the privilege level information is used to indicate the privilege level of the privileged state of the main logical core when the process performs the target operation. In this way, the main logic core can correctly handle the target operation based on these parameters.

In a possible implementation, the slave logical core can run acceleration engines and algorithms, such as one or more of the mySql process, graph calculation process, or encryption and decryption operators. Compared with running these processes on the main logical core, it can Improve computing speed.

In the second aspect, this application provides a device for switching the execution state of a process, and the device may be a CPU.

The device includes a processor and a memory; the memory is used to store a computer program; the processor is used to call the computer program stored in the memory to perform the following steps: if the process running in the slave logical core meets the first condition, the process in the slave logical core is suspended. process, and record the pause position of the process. The pause position is used to determine the execution position the next time the process is run from the logical core. The first condition is used to indicate that the process is to perform the target operation, and the target operation is in the execution state of the process. It can be executed when the main logical core is in the privileged state; the execution state of the process is switched from the user mode of the slave logical core to the privileged state of the main logical core; the process is run in the main logical core so that the process can perform the target operation.

In a possible implementation, when the processor records the pause position of the process, it is specifically used to: write the pause position information into the configuration space through the slave logical core, and the configuration space is used for information exchange between the master logical core and the slave logical core. Interaction.

In a possible implementation, the processor is also used to: switch the execution state of the process from the privileged state of the main logical core to the user state of the slave logical core; read the pause position information from the configuration space through the slave logical core; In the secondary logical core, the process continues from the pause position.

In a possible implementation, the first condition includes the process triggering a first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions; When the execution state is switched from the user state of the slave logical core to the privileged state of the master logical core, it is specifically used to: trigger the master logical core to run the process, so as to switch the execution state of the process from the user state of the slave logical core to the user state of the master logical core. state; determine the target privilege level corresponding to the first type of exception from the multiple privilege levels of the privileged state of the main logical core; switch the execution state of the process from the user mode of the main logical core to the target privilege level of the privileged state of the main logical core .

In one possible implementation, before switching the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, the processor is also used to: obtain the virtual memory corresponding to the target privilege level. Address; determine that the virtual memory address is not mapped to the physical memory address.

In a possible implementation, the first condition includes the process receiving an interrupt or triggering a RAS exception.

In a possible implementation, the processor is also used to: start a process in the main logical core; if the instruction set of the process belongs to the instruction set running from the slave logical core, record the starting position of the process, and trigger entry from the slave logical core Running status; in the slave logical core, start running the process from the starting position.

In a possible implementation, the processor is also used to: release hardware resources of the physical core occupied by the main logical core when running the process; where the hardware resources include memory resources and/or input and output resources.

In a possible implementation, the processor is also used to record one or more of the following information from the logical core: the reason for suspending the running process on the slave logical core, the execution parameters corresponding to the target operation, and the suspension of operation. The environment information of the process, or the privilege level information; where the privilege level information is used to indicate the privilege level of the privileged state of the main logical core when the process performs the target operation.

In a third aspect, this application provides a device for switching the execution state of a process, and the device may be a CPU.

The device includes a main logic core module and a slave logic core module. The slave logic core module is used to determine that when the process running in the slave logic core module meets the first condition, it pauses the running process and records the pause position of the process. The pause position is used for next time. The execution position is determined when the process is running in the slave logical core module, where the first condition is used to indicate that the process is to perform a target operation, and the target operation can be executed when the execution state of the process is in the privileged state of the main logical core module; the slave logical core module The core module is also used to switch the execution state of the process from the user state of the slave logical core module to the privileged state of the main logical core module; the main logical core module is used to run the process so that the process can perform target operations.

In one possible implementation, when the slave logical core module records the pause position of the process, it is specifically used to write the pause position information into the configuration space. The configuration space is used for information interaction between the master logical core module and the slave logical core module. .

In a possible implementation, the main logical core module is also used to switch the execution state of the process from the privileged state of the main logical core module to the user mode of the slave logical core module; the slave logical core module is also used to read from the configuration space. Get the information of the pause position and continue running the process from the pause position.

In a possible implementation, the first condition includes the process triggering the first type of exception, and the first type of exception includes other exceptions except reliability exceptions, availability exceptions, and serviceability RAS exceptions; from the specific use of the logical core module It is used to trigger the main logical core module to run the process, so as to switch the execution state of the process from the user mode of the slave logical core module to the user mode of the main logical core module; the main logical core module is specifically used for multiple privileged states of the slave main logical core module. The target privilege level corresponding to the first type of exception is determined among the privilege levels, and the target privilege level is used to switch the execution state of the process from the user state of the main logical core module to the privileged state of the main logical core module.

In a possible implementation, the main logical core module is also used to obtain the corresponding target privilege level before switching the execution state of the process from the user mode of the main logical core module to the target privilege level of the privileged state of the main logical core module. The virtual memory address; determine that the virtual memory address does not have a mapping relationship with the physical memory address.

In a possible implementation, the main logical core module is also used to start the process. If the instruction set of the process belongs to the instruction set running from the slave logical core, the starting position of the process is recorded and the slave logical core module is triggered to enter the running state. ;The slave logic core module is also used to run the process from the starting position.

In a possible implementation manner, the main logical core module releases the hardware resources of the physical core occupied when running the process; where the hardware resources include memory resources and/or input and output resources.

In a possible implementation, the slave logical core module is also used to record one or more of the following information: the reason for suspending the running process on the slave logical core, the execution parameters corresponding to the target operation, and the reasons for suspending the running process. Environment information, or privilege level information; where the privilege level information is used to indicate the privilege level of the privileged state of the main logical core when the process performs the target operation.

In a fourth aspect, embodiments of the present application provide a chip system, including: a processor and a memory. The processor is coupled to the memory. The memory is used to store programs or instructions. When the program or instructions are processed by the processor When executed, the chip system is caused to implement the method in the above first aspect or any possible implementation manner of the first aspect.

In a fifth aspect, the present application provides a computer program product. The computer program product includes a computer program or instructions. When the computer program or instructions are executed by a device, the first aspect or any possible implementation manner of the first aspect is implemented. Methods.

In a sixth aspect, the present application provides a computer-readable storage medium. Computer programs or instructions are stored in the computer-readable storage medium. When the computer program or instructions are executed by a computing device, the above-mentioned first aspect or any of the first aspects is implemented. method in one possible implementation.

In a seventh aspect, the present application provides a computing device, including a processor, the processor is connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that The computing device executes the method in the above first aspect or any possible implementation of the first aspect.

The technical effects that can be achieved by any one of the above-mentioned second to seventh aspects can be referred to the description of the beneficial effects in the above-mentioned first aspect, and will not be repeated here.

Description of the drawings

Figure 1 is a schematic diagram of an ARMv8-A architecture;

Figure 2 is a schematic diagram of the process of switching between AArch64 and AArch32 execution states;

Figure 3 is an architectural schematic diagram of a chip system provided by this application;

Figure 4 is a schematic diagram of the running processes in a Master logical core and a Slave logical core provided by this application;

Figure 5 is a schematic flow chart of an execution state switching method provided by this application;

Figure 6 is a schematic diagram of a startup process provided by this application;

Figure 7 is a schematic diagram of a method for switching the execution state of a process provided by this application;

Figure 8 is a schematic diagram of a Master logical core provided by this application trapping a process into a target privilege level;

Figure 9 is a schematic diagram of yet another method for switching the execution status of a process provided by this application;

Figure 10 is a schematic diagram of another method for switching the execution status of a process provided by this application;

Figure 11 is a schematic flowchart of yet another execution state switching method provided by this application.

Detailed ways

In order to better explain the embodiments of this application, the relevant terms or technologies in this application will first be explained:

(1)Procedures and processes

A program is an ordered collection of instructions, it is just a static entity.

A process is the execution of a program on some data set. A process is a dynamic entity with its own life cycle. Processes are created due to creation, run due to scheduling, placed in a waiting state due to waiting for resources or events, and canceled due to completion of tasks. A process reflects the entire dynamic process of a program running on a certain data set.

(2) User mode and kernel mode

When a process is executing user code, it is in the user running state (also called user mode). When a process is trapped in kernel code for execution due to a system call, the process is in the kernel running state (also called kernel state). The executed kernel code will use the kernel stack of the current process, and each process has its own kernel stack.

The user runs a program, and the process created by the program starts by running its own code in user mode. When the process needs to perform operations such as file operations and network data transmission, the kernel code is called through system calls such as write and send. The process enters the kernel address space to execute kernel code to complete the corresponding operation. After the kernel mode process is executed, it will return to the user mode. User-mode processes cannot manipulate the kernel address space at will.

(3)CPU, physical core, logical core

CPU is not equal to physical core, nor is it equal to logical core.

The physical core (physical core/processor) is a visible, real CPU core. The physical core has independent circuit components and L1 and L2 caches, and can execute instructions independently.

Logical core/processor (LCPU): A core at the logical level within the same physical core.

Among them, a CPU can have multiple physical cores. A physical core can be divided into multiple logical cores.

(4) Real-time operating system (kernel) refers to the core part of most operating systems. It consists of the parts of the operating system that manage memory, files, peripherals, and system resources.

(5) Executable and Linkable Format (ELF) files refer to target files on Unix and X86-64 Linux. The target file refers to the computer file used to store the target code. The target file can contain machine code, data used by the code when running, debugging information, etc. It is the process of generating program files from source code files. mid product.

(6) Synchronous operations and asynchronous operations

Synchronous operation means that when the caller calls, it needs to wait for the call to return the result before continuing to execute.

Asynchronous operations are the opposite of synchronous operations. After the caller issues a call, it does not need to wait for the call result, but continues to perform subsequent operations. The callee notifies the caller through the status, or handles the call by calling back the function.

(7) Reliability, availability, durability (RAS)

Reliability means that the system must be as reliable as possible without unexpected crashes, restarts or even physical damage to the system. Availability refers to the fact that the system must be able to work as long as possible without going offline. Even if some minor problems occur in the system, it will not affect the normal operation of the entire system. Serviceability refers to the ability of the system to provide convenient diagnostic functions, such as system logs, dynamic detection and other means to facilitate system diagnosis and maintenance operations by managers, so as to detect and repair errors as early as possible. As a whole, the role of RAS is to ensure that the entire system runs reliably for as long as possible without going offline, and has a sufficiently powerful fault-tolerant mechanism.

(8) Firmware is generally stored in the electrically erasable programmable ROM (EEPROM) or FLASH chip in the device. Firmware is, for example, the basic input/output system BIOS (basic input/output system) on the computer motherboard.

(9) Register is an integral part of the central processing unit. Registers are high-speed storage components with limited storage capacity. Registers can be used to temporarily store instructions, data and addresses. The program status saving register (saved program status register, SPSR) is used to save the status of the program status register (current program status register, CPSR) so that the working status when the exception occurs can be restored after an exception returns. When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. When exiting from an abnormal interrupt, SPSR can be used to restore CPSR.

Based on the above related terms or technical explanations, the scenarios applicable to this application are explained as follows.

The CPU physical core can include a master logical core and a slave logical core. The CPU physical core can run multiple processes, and the multiple processes can run on the Master logical core or the Slave logical core. For example, if the Master logical core is an ARM64 logical core and the Slave logical core is an ARM32 logical core, the ARM64 process can run in the ARM64 logical core, and the ARM32 process can run in the ARM32 logical core. Under normal circumstances, no matter what kind of logical core a process is running in, it can be started by the Master logical core. If the Master logical core determines that the process needs to run on the Slave logical core, it can call the Slave logical core so that the process Runs in the Slave logical core.

As follows, taking the Master logical core as an ARM64 logical core and the Slave logical core as an ARM32 logical core as an example to illustrate how the ARM64 logical core starts the ARM32 process and runs the ARM32 process in the ARM32 logical core.

For example, in the ARMv8 architecture, two execution states of AArch32 (or ARM32) and AArch64 (or ARM64) can be supported at the same time. Among them, the AArch64 execution state supports the A64 instruction set and can run ARM64 processes. AArch32 execution state supports T32 and A32 instruction sets and can run ARM32 processes.

The concept of privilege level in ARMv8-A is called exception level (EL, exception level), which is A logical division of privilege levels at which a program runs. Exception levels are divided into the following four types:

EL0: Normal user program;

EL1: operating system kernel;

EL2: virtual machine monitor;

EL3: Low-level firmware, including Secure Monitor.

Among them, the larger the privilege level number, the higher the privilege. Typically, a piece of software, such as an application, operating system kernel, or virtual machine monitor, occupies only one exception level.

The ARMv8-A architecture can be seen in Figure 1. The execution state of the ARM32 logical core is AArch32, and the execution state of the ARM64 logical core is AArch64. Among them, AArch32 can correspond to the EL0 privilege level, and AArch64 can correspond to the EL0 and EL1 privilege levels. Or it can be understood that at the EL0 privilege level, user-mode processes can be run in AARCH64 and AARCH32 execution states; at EL1 privilege level, kernel-mode processes can be run in the AArch64 execution state.

Furthermore, the ARMv8-A architecture can have the following characteristics:

(1) The A32 and T32 instruction sets supported by AArch32, and the A64 instruction set supported by AArch64 can be encapsulated through execution state.

(2) The CPU must be in the execution state of AArch32 or AArch64 at any time. When switching between the two execution states of AArch32 and AArch64, the CPU needs to fall into a high privilege level through an exception.

(3) AArch32 and AArch64 are tightly coupled, and they can share registers.

(4) AArch32 and AArch64 cannot call each other (for example, functions in the A64 instruction set cannot call functions in the A32 instruction set or T32 instruction set), and AArch32 and AArch64 cannot be used as extensions of each other.

(5) In order to implement AArch64 to support AArch32 exception handling, add a set of ARM32EL0 exception processing entries to the exception vector table. For example, the exception vector table includes the correspondence between exceptions and exception handlers. AArch32 needs to trap the low privilege level to the high privilege level when an exception occurs. AArch64 accesses the exception vector table when the high privilege level determines the exception handler that needs to be scheduled.

Figure 2 illustrates a process of switching between AArch64 and AArch32 execution states provided by this application. Specifically, the process is to run an ARM32 executable program (which can be referred to as a program) in the AArch64 execution state.

Step 201. In the AArch64 execution state, the EL0 user state loads the ARM32 process and will fall into the EL1 kernel state. The ELF file format is parsed in the EL1 kernel and it is found that the EL0 user state needs to run the program of the A32 instruction set. Then, return to the EL0 user state. When in the state, it will switch to the AArch32 execution state by setting the SPSR, that is, the execution state switches from AArch64 to AArch32.

Step 202: When the ARM32 process running in the AArch32 execution state needs to handle an exception, it needs to do so by falling into the EL1 kernel state, that is, the execution state is switched from AArch32 to AArch64 again. After handling the exception, the EL1 kernel state returns to the AArch32 execution state of EL0 as required. Or, after the ARM32 process running in the AArch32 execution state finishes running, it needs to be completed by falling into the EL1 kernel state.

In this way, the logical core run by the ARM32 process needs to frequently switch between the ARM64 logical core and the ARM32 logical core. This abnormal switching requires the hardware to complete a lot of work. Switching between the ARM64 logic core and the ARM32 logic core needs to be based on the exception recorded in the exception vector table and the handler corresponding to the exception. The exception vector table is stored in a register, and the exception vector table needs to occupy a large number of registers. The ARM64 logic core and the ARM32 logic core share registers, and they are tightly coupled and cannot evolve independently.

This application provides a method and device for switching the execution state of a process, which is used to flexibly switch the execution state of two logical cores. Under the premise of running status, the two logical cores are decoupled, so that one of the logical cores can be independently evolved.

In order to facilitate the description of the switching method in this application, the system architecture applicable to this application is first explained. Figure 3 is a schematic diagram of the architecture of a chip system. The chip system includes multiple CPU physical cores. Each CPU physical core can include two logical cores, which can be represented as Master logical core and Slave logical core respectively.

The Master logical core can be used to perform privileged state operations, and the Slave logical core can be used to perform user state operations. Among them, multiple privilege levels in the privileged state are higher than those in the user state. For example, the Master logical core is ARM64. The privileged state implemented by the Master logical core corresponds to the three privilege levels of EL1, EL2 and EL3. The Slave logical core implements the privileged level of the user state. Among them, the three privileged levels of EL1, EL2 and EL3 are higher than User mode privilege level.

In addition, the Master logical core can also be used to perform user-mode operations, which can achieve user-mode privilege levels. Still taking the Master logical core as ARM64 as an example, the user mode implemented by the Master logical core includes the EL0 privilege level. The user-mode privilege level implemented by the Master logical core can be the same privilege level as the user-mode privilege level implemented by the Slave logical core.

For example, the user mode program can run in the Master logical core according to its instruction set, or it can also run in the Slave logical core. System software (such as Kernel/Hypervisor/Firmware) can only run in the Master logical core.

Furthermore, the Master logic core and the Slave logic core use different instruction sets. Among them, the instruction set of the Master logic core can be the current mainstream instruction set such as X86 or ARM. The instruction set of the slave logic core can be a self-developed instruction set. The computing power of the Slave logical core can be higher than the computing power of the Master logical core.

Among them, the process running on the Slave logical core (hereinafter referred to as the process) includes an executable code segment. The executable code segment may include two parts: a springboard code segment (which can be expressed as trampoline code in English) and a main body code segment.

Among them, the springboard code segment runs in the Master logical core and is used to call the Slave logical core to run the process. It can be understood that since the loading of the process occurs in the Master logical core and the running of the process occurs in the Slave logical core, a springboard code segment in the Master logical core is needed to switch the process from running on the Master logical core to running on the Slave logic. nuclear.

The main code segment runs in the Slave logical core, where the main code segment is the main code of the running process.

There is a configuration space between the Master logical core and the Slave logical core. This configuration space can be understood as the interactive interface between the two logical cores. The configuration space can be a register group or a special memory space. This configuration space can be used for information exchange between the Master logical core and the Slave logical core. For example, when the Master logical core starts a process, it can determine that the process needs to run in the Slave logical core, and then execute the Slave logical core. The relevant parameters of the process are written into the configuration space. The Slave logic core reads the relevant parameters from the configuration space and starts executing the process based on the read parameters.

Each CPU physical core corresponds to an extra-core resource, such as a cache or a memory management unit (MMU).

Multiple CPU physical cores and corresponding extra-core resources of the multiple CPU physical cores can be packaged together in a chip system, and the chip system can be connected to memory and peripherals.

Taking the Master logical core as an ARM64 logical core as an example, explain the processes running in the Master logical core and Slave logical core. Among them, the Master instruction set in the ARM64 logical core can also be called the A64 instruction set, and the process running on the ARM64 logical core can also be called the A64 process. As shown in Figure 4, the chip system corresponds to the user state, privileged state and hardware part. The user-mode processes and system software (such as Kernel/Hypervisor/Firmware) of the A64 instruction set run on the ARM64 logical core, and the user-mode processes (ie processes) of the Slave instruction set run on the Slave logical core.

The method for switching the execution state of the process in this application is explained as follows. For this method, please refer to the flow chart shown in Figure 5.

Step 501: Start the process on the Master logical core and determine that the process needs to run on the Slave logical core. Start the Slave logical core so that the Slave logical core runs the process. Among them, when running a process on the Slave logical core, the process can only perform user-mode operations.

Step 502: When it is determined that the process needs to perform operations in the privileged state, the execution state of the process is switched from the user state to the privileged state. Correspondingly, the process needs to be switched to run in the Master logical core.

Step 503: After the process in the Master logical core processes the privileged state operation, the execution state of the process can be switched from the privileged state back to the user state. Correspondingly, the process is switched back to the Slave logical core to run.

When the execution state of the above process switches from the privileged state to the user state, or from the user state to the privileged state, the Master logical core and the Slave logical core can exchange information with each other through the configuration space.

Figure 6 is a schematic diagram of a Master logical core startup process provided by this application. The above-mentioned step 501 is explained with reference to Figure 6, in which the text in the dotted box may represent the actions performed by the Master logical core or the Slave logical core.

The Master logical core starts the running process in the user state and traps the process from the user state to the privileged state. The Master logical core loads the process data from memory.

Among them, the data of the process such as the code segment/text segment, data segment, executable file, etc. of the process. A code segment is usually an area of memory used to store program execution code. The data segment usually refers to the memory area used to store initialized global variables in the program. An executable file is, for example, an ELF file.

For example, the executable file of the process records the identification of whether the process needs to run on the slave logical core. Correspondingly, the Master logical core determines whether the process needs to run on the Slave logical core based on the identification.

For another example, the Master logical core determines, based on the code segment, that the instruction set executed by the process belongs to the instruction set run by the Slave logical core, and then determines that the process needs to run on the Slave logical core.

If the Master logical core determines that the process needs to run in the Slave logical core, it can return the process from the privileged state to the user mode of the Slave logical core, so that the Slave logical core executes the process in the user mode. Specifically, when the Master logical core returns the process from the privileged state to the user state of the Slave logical core, it can return the process to the entry of the springboard code segment in the Master logical core, and write the entry of the process through the springboard code segment. Enter the configuration space, thereby triggering the Slave logical core to start executing the process from this entry.

Specifically, the Master logical core can write the starting position (or starting position information) of the process into the configuration space through the springboard code segment, and then the Master logical core operates the configuration space through the springboard code segment to trigger the startup command (available in English). This is called the slave call instruction), thereby starting the Slave logical core through the slave call instruction. Correspondingly, the slave logic core reads the starting position from the configuration space and starts the process based on the read starting position.

In addition, after calling the slave call instruction, the Master logical core can release the hardware resources of the physical core occupied by the Master logical core when running the process. The hardware resources can include memory resources, input/output (I/O) One or more resources. In this way, this part of the released hardware resources can be reused to execute other processes, which helps to make full use of the hardware resources.

Further, the Master logic core writes the position of the next instruction of the slave call instruction (this position can be recorded as master.pc) into the configuration space. This master.pc can be used by the Master logical core to know from which position to start executing the process when it needs to execute the process again. For this implementation, please refer to the description of step 502 in the following embodiment. As shown below, for the convenience of description, the next instruction of the slave call instruction can be called the master.pc instruction.

When the Slave logical core executes a process, there may be situations where the process satisfies the first condition. The first condition can be used to indicate that the process needs to perform an operation in a privileged state. Here, the operation in the privileged state can be called a target operation. That is, the first condition can be used to indicate that the process needs to perform the target operation. Further, the Slave logic core needs to suspend the current running The process in the Slave logical core is then switched to be run by the Master logical core, so that the process running in the Master logical core can perform the target operation.

Furthermore, based on different types of target operations, the pauses triggered by the target operations can be divided into exceptions (Exception) and interruptions (Interruption).

Exceptions refer to events from within the CPU executing instructions. Abnormalities can be divided into first-type exceptions and second-type exceptions. The first-type exceptions can be ordinary exceptions, and the second-type exceptions can be RAS exceptions. RAS exceptions include physical damage to memory pages. Common exceptions are exceptions other than RAS exceptions. Common exceptions include system calls (or syscalls for short), page faults, instruction faults, etc.

Interrupts refer to events that occur other than when the CPU executes instructions, such as clock interrupts, serial port interrupts, network interrupts, I/O interrupt stops, etc. Take the clock interrupt as an example. The clock interrupt indicates that a fixed time slice has arrived, allowing the CPU to process timing, start scheduled tasks, etc.

The above step 502 is explained as follows based on three situations: ordinary exception, interruption, and RAS exception.

1. Common exceptions

Figure 7 shows a schematic diagram of a method for switching the execution state of a process when a process triggers a common exception. The text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.

During the running of the Slave logical core, the process triggers a common exception because it needs to perform the target operation. The slave logical core needs to write the running context (or common exception information) of the process into the configuration space.

Ordinary exception information may include one or more of the following: privilege level information, instruction location that triggered the exception, exception cause, exception occurrence address, exception parameters, register information, etc.

The privilege level information is used to indicate the privilege level corresponding to the target operation (which can be called the target privilege level), that is, which privilege level the Master logical core needs to use to handle this exception. For example, if the target operation is a system call, the target privilege level is EL1.

The instruction location that triggers the exception can be considered as the location where the process was interrupted, and can be recorded as slave.pc. When the Slave logical core resumes execution, the Slave logical core can continue execution from this location slave.pc. Among them, the instruction corresponding to the location slave.pc can be called the slave.pc instruction.

Exception cause indicates the reason for suspending the running process on the secondary logical core, or indicates the reason for the exception, such as system call, page fault, instruction failure, etc.

The address where the exception occurred, such as the location in memory being accessed.

Exception parameters, such as parameters that need to be passed in system calls.

Register information is used to indicate the running environment information in the Slave logical core when the running process is suspended in the Slave logical core. This running environment information can be used by the Slave logical core to continue executing the process. Register information is, for example, SPSR information.

Correspondingly, the hardware resources corresponding to the Slave logical core can be released (Retired) at the instruction location that triggers the target operation. The Slave hardware unit switches the process from running on the Slave logical core to running on the Master logical core. Correspondingly, the Master logical core reads the location master.pc in the configuration space, and then continues execution from the next instruction of the slave call instruction in the springboard code segment (ie, the master.pc instruction) based on the location master.pc.

It can be understood that the execution state of the process is switched from the user state of the Slave logical core to the user state of the Master logical core. The Master logical core needs to further switch the process from the user state of the Master logical core to the privileged state of the Master logical core. . Specifically, the Master logical core can also read the common exception information of the process in the configuration space, and according to the common exception information of the process, the execution state of the process is dropped from the user state of the Master logical core to the privileged state of the Master logical core. Among them, the Master logical core can determine whether to trap the process based on the privilege level information in the ordinary exception information. Enter the target privilege level of the privileged state.

After the process falls into the target privilege level, the Master logic core further performs the target operation based on the exception cause, exception occurrence address, exception parameters and other information in the ordinary exception information, that is, handles the ordinary exception.

As follows, the common exceptions are system calls and page faults as examples.

1. System call

Further, the exception parameters may include system call identification (syscall id) and system call input parameters.

The Master logical core can read the system call identifier and system call input parameters from the common exception information in the configuration space, construct a system call based on these two parameters, and then issue the system call, that is, the Master logical core privileged state sees is the converted system call. After the system call is executed, the Master logical core can write the return value of the system call into the configuration space. In this way, the Slave logical core can read the return value of the system call from the configuration space.

For example, the Master logical core can construct the system call according to the application binary interface (ABI) rules of the corresponding architecture of the Master logical core, so that it is applicable to different CPUs. Correspondingly, the Master logical core still writes the return value of the system call to the configuration space according to the ABI rules.

2. Page error

Further, the exception parameters may include the virtual page address corresponding to the page fault.

The Master logical core can read the virtual page address from the common exception information in the configuration space, apply for a physical page address for the virtual page address, and then establish a mapping relationship between the virtual page address and the physical page address, and update the page table. The virtual page address can also be called a virtual memory address, and the physical page address can also be called a physical memory address.

It should be pointed out that since the number of common exceptions caused by the process is relatively large, this application can determine the privilege levels corresponding to these common exceptions for different common exceptions. It can be understood that one privilege level can correspond to a variety of common exceptions. For example, the EL1 privilege level corresponds to system calls, page faults, instruction failures, etc. When such exceptions occur, the Master logical core can trap the process into the EL1 privilege level for processing. .

In one possible implementation, the Master logical core changes the execution state of the process from the user state of the Master logical core to the target privilege level of the Master logical core's privileged state. This can be achieved by constructing a special exception. For details, please refer to the trapping method shown in Figure 8 .

It should be noted in advance that two virtual page addresses can be added in the real-time operating system, and the two virtual page addresses respectively correspond to two privilege levels of the privileged state (specifically, the kernel state). For example, the two privilege levels in the kernel state are EL1 privilege level and EL2 privilege level. Among them, virtual page address 1 corresponds to the EL1 privilege level, and virtual page address 2 corresponds to the EL2 privilege level. Further, the two virtual page addresses do not establish a mapping relationship with the physical page addresses.

Correspondingly, the Master logical core can select the target privilege level corresponding to the ordinary exception from multiple privilege levels corresponding to the privileged state based on the type of ordinary exception triggered by the Slave logical core; and then determine the target privilege level from multiple virtual page addresses. The virtual page address corresponding to the level. The Master logical core accesses the virtual page address corresponding to the target privilege level by executing the page access instruction and determines that the virtual page address does not establish a mapping relationship with the physical page address, so an exception (i.e., page fault) is triggered. Subsequently, the Master logical core falls from the user state to the target privilege level in the privileged state.

For example, the Master logical core determines that the exception triggered by the process is a system call, and the Master logical core determines that the process needs to be trapped into the EL1 privilege level based on the system call. The master logical core accesses virtual page address 1 and determines that the current virtual page address 1 does not correspond to the physical page address, that is, the virtual page address 1 access error. Subsequently, the Master logical core triggers a page fault exception and traps the process into the EL1 privilege level. In this way, the process runs at the EL1 privilege level of the Master logical core, and the Master logical core can perform the target operation, that is, process the system call.

Here, there is no need to perform page fault processing for page faults triggered by the Master logical core accessing the virtual page address, such as Therefore, the Master logical core can repeatedly trigger page fault exceptions, thereby trapping the execution state of the process from the user state of the Master logical core to the target privilege level of the Master logical core's privileged state.

Furthermore, the page fault here is used to change the execution state of the process from the user state of the Master logical core to the target privilege level of the privileged state of the Master logical core. This page fault is different from the one triggered when the Slave logical core runs the process. Page fault, the latter is an exception that really needs to be handled during the running of the process.

After the Master logic core completes the target operation in the privileged state (or is understood to have handled ordinary exceptions), it can return to the springboard code segment. Specifically, the Master logic core can return to the page access instruction in the springboard code segment. After the page access instruction, the Master logical core continues to execute the slave call instruction, thereby triggering the operation of the Slave logical core. The Slave logical core continues execution from the interrupted position slave.pc. Furthermore, the Slave logical core can read the register information from the ordinary exception information in the configuration space, and based on the read register information, restore the running environment information of the process before the Slave logical core triggered the exception.

2. Interruption

Figure 9 shows a schematic diagram of a method for switching the execution state of a process when the process receives an interrupt. The text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.

The process receives an interrupt during the running of the Slave logical core. The Slave logical core needs to write the running context (or interrupt information) of the process into the configuration space.

The interrupt information may include one or more of the following: privilege level information, instruction location where the interrupt was received, interrupt cause, interrupt occurrence address, interrupt parameters, register information, etc. Among them, the privilege level information, interrupt parameters, register information, and interrupt occurrence address can be found in the description of the running context in the above common exception.

The instruction location that received the interrupt can also be recorded as slave.pc. When the Slave logical core resumes execution, the Slave logical core can continue execution from this location slave.pc.

Interruption reason indicates the cause of the interruption, such as clock interruption, serial port interruption, network interruption, etc.

Since interrupts are asynchronous events and need to be processed quickly, the hardware unit of the Slave logical core can trap the execution state of the process into a privileged state. Here, the hardware unit of the Slave logical core can also determine which privilege level the process will fall into in the privileged state based on the type of interrupt, such as falling into the EL1 privilege level or the EL2 privilege level.

From the perspective of the Master logical core, the location where the interrupt occurs is master.pc. The explanation is that the Slave logical core undergoes many operations during the execution of the salve.call instruction, such as the Master logical core sleeping, the Slave logical core triggering a running instruction, etc. For the Master logic core, the time when an interrupt occurs is during the execution of salve.call. The time point when the Master logic core responds to the interrupt is after the salve.call instruction is executed and the next instruction (ie, the master.pc instruction) is executed. before execution.

After the Master logical core completes the target operation in the privileged state (or is understood to have processed the interrupt), the Master logical core returns to master.pc in the springboard code segment. Subsequently, the Master logical core continues to execute the slave call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.

3. RAS abnormality

Figure 10 shows a schematic diagram of a method for switching the execution state of a process when a process triggers a RAS exception. The text in the dotted box can represent the actions performed by the Master logical core or the Slave logical core.

RAS exceptions can be further divided into synchronous abort (SErrors for short) and asynchronous abort (SEI for short).

Among them, SErrors are related to the execution of instructions. The return address maintained by SErrors when entering the exception state accurately reflects the instruction in which the exception occurred, and may occur at any step during the execution of the instruction. For example, failure in the instruction fetch phase, failure in the decoding phase, failure in the instruction execution phase, etc. SErrors are similar to ordinary exceptions and are a synchronous event.

SEI has nothing to do with the executed instructions. SEI comes from an external memory system or an error on the bus, such as an unrecoverable error correcting code error (ECC error). SEI is similar to an interrupt and is an asynchronous event.

When the process is running on the Slave logical core, a RAS exception is triggered because it needs to perform the target operation. The slave logical core needs to write the running context of the process (or RAS exception information) into the configuration space.

RAS exception information may include one or more of the following: privilege level information, instruction location that triggers RAS exception, RAS exception cause, RAS exception occurrence address, RAS exception parameters, register information, etc.

Among them, the privilege level information, RAS exception parameters, register information, and RAS exception occurrence address can be found in the description of the running context in the above common exceptions.

The instruction location that triggers the RAS exception can also be recorded as slave.pc. When the Slave logical core resumes execution, the Slave logical core can continue execution from the slave.pc.

RAS abnormality reason, indicating the cause of RAS abnormality, such as error correction code error, etc.

The hardware unit of the Slave logical core can drop the execution state of the process from the original user state to the privileged state. Among them, the privileged state can specifically be a firmware state. For example, the firmware state corresponds to the EL3 privilege level. Correspondingly, the hardware unit of the Slave logical core can trap the execution state of the process to the EL3 privilege level. In RAS exceptions, the user state can also be called the EL0 privilege level in the privileged state. The EL0 privilege level is lower than other privilege levels in the privileged state.

From the perspective of the privileged state of the Master logical core, the RAS exception occurs in master.pc. The explanation is that the salve logical core undergoes many operations during the execution of the salve.call instruction, such as the Master logical core sleeping, the Slave logical core triggering a running instruction, etc. For the Master logical core, the time when a RAS exception occurs is during the execution of salve.call. The time point when the Master logical core responds to the RAS exception is after the salve.call instruction is executed, and the next instruction (i.e. the master.pc instruction ) before execution.

The Master logical core handles RAS exceptions in the EL3 privilege level and obtains the RAS exception processing results. The RAS exception processing result can be used to indicate whether the RAS exception is recoverable. The Master logical core returns from the EL3 privilege level to the EL1 privilege level, or in other words, returns from the firmware state to the kernel state.

Correspondingly, the Master logical core obtains the RAS exception processing result at the EL1 privilege level. When it is determined that the RAS exception is recoverable based on the RAS exception processing result, the Master logical core performs the target operation at the EL1 privilege level and returns to the master recorded in the configuration space. The instruction corresponding to the .pc position (that is, the master.pc instruction). When it is determined that the RAS exception is unrecoverable based on the RAS exception processing result, the Master logical core performs panic kernel processing at the EL1 privilege level.

In one possible way, when the Master logical core handles RAS exceptions in the EL3 privilege level, the firmware of the Master logical core may perform the following steps (a) to (c):

(a) Save the user mode context and restore the EL3 privilege level context.

(b) Read the RAS exception information in the configuration space, and handle the RAS exception based on the RAS exception information, such as trying to repair the memory page.

(c) Save the EL3 privilege level context, restore the user mode context, and set the ESR_EL1, FAR_EL1, SPSR_EL1 and other registers. Since the EL1 privilege level obtains some exception status through the ESR_EL1, FAR_EL1, SPSR_EL1 registers, the purpose of setting these registers is to enable The EL1 privilege level believes that the source of the exception is the user mode. After the EL1 privilege level handles the exception, it returns to the user mode through the ERET instruction instead of returning to the Fireware corresponding to the EL3 privilege level.

After the privileged state of the Master logical core processes the target operation, the Master logical core returns to the master.pc instruction in the springboard code segment. Subsequently, the Master logical core continues to execute the slave call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.

It should be noted that the above-mentioned general exception information, interrupt information, and RAS exception information can be collectively referred to as the running context of the process. Among them, the exception cause, interrupt cause, and RAS exception cause can be collectively referred to as the suspension of the running process on the Slave logical core. Reason, that is, the reason for the suspension of the process; exception parameters, interrupt parameters, and RAS exception parameters can be collectively referred to as the execution parameters corresponding to the target operation of the process; the instruction location that triggers the exception, the instruction location that receives the interrupt, and the instruction location that triggers the RAS exception. It can be collectively referred to as the location where the process was interrupted, or the pause location of the process (slave.pc), or the information of the pause location of the process. It can also be understood that the running context of a process may include one or more of the following: the pause position of the process on the Slave logical core, the reason for the suspension of the process on the Slave logical core, execution parameters corresponding to the target operation, and register information. (ie, environment information when the running process is suspended) or privilege level information.

In addition, it should be added that only the main steps in the relevant embodiments are marked in the above-mentioned Figures 6 to 10, and the step numbers in each figure only indicate the sequence of each action in the figure in which they are located.

In order to better explain the execution positions of the Master logical core and the Slave logical core in the case of ordinary exceptions, interruptions or RAS exceptions in the embodiments of this application, continue the explanation with reference to the example in Figure 11, where the code segment on the left in Figure 11 can be considered as the Master The springboard code segment contained in the logic core.

The Slave logical core runs the process and determines that the process triggers a common exception. The Slave logical core switches the execution state of the process from the user mode of the Slave logical core to the user mode of the Master logical core. The Master logical core starts executing from the instruction at the master.pc location (i.e., the master.pc instruction), and determines that it needs to go to the EL1 privilege level for processing based on the common exception, so it accesses the virtual page address 1 corresponding to the EL1 privilege level (shown as in Figure 11 page1), and then, after the Master logical core triggers the page fault exception corresponding to page1, the execution state of the process falls into the EL1 privilege level to perform the target operation. After completing the target operation, the Master logic core returns to the instruction that accesses page1 (that is, the page access instruction), and then returns to instruction 1. Further, the Master logical core calls the slave.call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.

The Slave logical core runs the process and determines that the process has received an interrupt. The hardware unit of the Slave logical core changes the execution state of the process from the user state of the Slave logical core directly to the privileged state of the Master logical core (such as EL1 privilege level). The Master logical core runs the process so that the process performs the target operation. After the process completes the target operation, it returns to the instruction at the master.pc location (that is, the master.pc instruction), and then returns to instruction 1. Further, the Master logical core calls the slave.call instruction to trigger the Slave logical core to run, and the Slave logical core continues execution from the interrupted location slave.pc.

The Slave logical core runs the process and determines that the process triggers a RAS exception. The hardware unit of the Slave logical core changes the execution state of the process from the user state of the Slave logical core directly to the privileged state of the Master logical core (such as EL3 privilege level). The Master logical core runs the process so that the process performs the target operation. After the process completes the target operation, it returns to the instruction at the master.pc location (that is, the master.pc instruction), and then returns to instruction 1. The Master logical core calls the slave.call instruction to trigger the Slave logical core to run. The Slave logical core continues execution from the interrupted location slave.pc.

In the above technical solution, the Master logic core and the Slave logic core exchange information through the configuration space to realize the decoupling of the Master logic core and the Slave logic core, so that the Master logic core and the Slave logic core can develop independently, that is, Without destroying the architectural semantics/instruction space corresponding to the Master logical core, the independent evolution of the instruction set corresponding to the Slave logical core can be achieved. In this way, the Slave logical core can run acceleration engines and algorithms, such as mySql One or more of the processes, graph calculation processes, or encryption and decryption operators can increase the computing speed compared to the Master logical core.

Further, when a process running on the Slave logical core needs to perform a target operation, the Slave logical core can write the running context of the process into the configuration space. The running context includes the pause location corresponding to the paused process of the Slave logical core. Correspondingly, after the Master logical core completes the target operation of the process, it can continue to start the Slave logical core to run the process. Subsequently, the Slave logical core can read the pause position from the configuration space and continue to execute the process at the pause position. process. In this way, the process can switch the running state between the Master logical core and the Slave logical core.

It should be added that in this application, the relationship between the logical core, the process and the target operation can be understood as the process runs in the logical core (Slave logical core or Master logical core), and the process executes the target operation, that is, its runtime The logical core where it is located (such as the Master logical core) performs the target operation.

Based on the above content and the same concept, this application provides a computer program product. The computer program product includes a computer program or instructions. When the computer program or instructions are executed by a device, the method in the above method embodiment is implemented.

Based on the above content and the same concept, this application provides a computer-readable storage medium. Computer programs or instructions are stored in the computer-readable storage medium. When the computer program or instructions are executed by a computing device, the method in the above method embodiment is implemented. .

Based on the above content and the same concept, this application provides a computing device, including a processor. The processor is connected to a memory. The memory is used to store computer programs. The processor is used to execute the computer program stored in the memory, so that the computing device implements the above method. Methods in Examples.

It can be understood that the various numerical numbers involved in the embodiments of the present application are only for convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the protection scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A method for switching execution states of a process, which is characterized in that it is applied to a central processing unit (CPU). The CPU includes a physical core, and the physical core includes a master logical core and a slave logical core. The method includes:

If the process running on the slave logical core meets the first condition, the process is suspended in the slave logical core, and the pause position of the process is recorded. The pause position is used for the next time the slave logical core is used. The execution position is determined when the process is running in the core, wherein the first condition is used to indicate that the process is to perform a target operation, and the target operation is in the privileged state of the main logical core when the execution state of the process is can be executed;

Switch the execution state of the process from the user state of the slave logical core to the privileged state of the main logical core;

The process is run in the main logical core, so that the process performs the target operation.
The method of claim 1, wherein recording the pause position of the process includes:

The information about the pause position is written into a configuration space through the slave logic core, and the configuration space is used for information interaction between the master logic core and the slave logic core.
The method of claim 2, further comprising:

Switch the execution state of the process from the privileged state of the master logical core to the user state of the slave logical core;

Read the information of the pause position from the configuration space through the slave logic core;

In the slave logical core, the process continues to run from the pause position.
The method according to any one of claims 1 to 3, characterized in that the first condition includes the process triggering a first type of exception, and the first type of exception includes reliability exception, availability exception, and availability exception. Exceptions other than service RAS exceptions;

Switching the execution state of the process from the user state of the slave logical core to the privileged state of the main logical core includes:

Triggering the main logical core to run the process to switch the execution state of the process from the user mode of the slave logical core to the user mode of the main logical core;

Determine the target privilege level corresponding to the first type of exception from multiple privilege levels of the privileged state of the main logical core;

Switch the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core.
The method of claim 4, wherein before switching the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core, include:

Obtain the virtual memory address corresponding to the target privilege level;

It is determined that the virtual memory address does not establish a mapping relationship with the physical memory address.
The method according to any one of claims 1 to 3, wherein the first condition includes the process receiving an interrupt, or the process triggering a RAS exception.
The method according to any one of claims 1 to 6, characterized in that the method further includes:

Start the process in the main logical core;

If the instruction set of the process belongs to the instruction set running from the slave logical core, record the starting position of the process and trigger the slave logical core to enter the running state;

In the slave logical core, the process is run starting from the starting position.
The method according to any one of claims 1 to 7, characterized in that the method further includes:

Release the hardware resources of the physical core occupied by the main logical core when running the process;

Wherein, the hardware resources include memory resources and/or input and output resources.
The method according to any one of claims 1 to 8, characterized in that the method further includes:

One or more of the following information is recorded through the slave logic core:

The reason why the process is suspended on the slave logical core, the execution parameters corresponding to the target operation, the environment information when the process is suspended, or privilege level information; wherein the privilege level information is used to indicate The privilege level of the privileged state of the main logical core when the process performs the target operation.
An execution state switching device, characterized in that it includes a processor and a memory;

The memory is used to store computer programs;

The processor is used to call the computer program stored in the memory to perform the following steps:

If the process running on the slave logical core meets the first condition, the process is suspended in the slave logical core, and the pause position of the process is recorded. The pause position is used for the next time the slave logical core is used. The execution position is determined when the process is running in the core, wherein the first condition is used to indicate that the process is to perform a target operation, and the target operation is in the privileged state of the main logical core when the execution state of the process is can be executed;

Switch the execution state of the process from the user state of the slave logical core to the privileged state of the main logical core;

The process is run in the main logical core, so that the process performs the target operation.
The device according to claim 10, wherein when the processor records the pause position of the process, it is specifically configured to: write the information of the pause position into the configuration space through the slave logical core, so The configuration space is used for information interaction between the master logic core and the slave logic core.
The device of claim 11, wherein the processor is further configured to:

Switch the execution state of the process from the privileged state of the master logical core to the user state of the slave logical core;

Read the information of the pause position from the configuration space through the slave logic core;

In the slave logical core, the process continues to run from the pause position.
The device according to any one of claims 10 to 12, wherein the first condition includes the process triggering a first type of exception, and the first type of exception includes reliability exception, availability exception, and availability exception. Exceptions other than service RAS exceptions;

When the processor switches the execution state of the process from the user state of the slave logical core to the privileged state of the main logical core, it is specifically used to:

Triggering the main logical core to run the process to switch the execution state of the process from the user mode of the slave logical core to the user mode of the main logical core;

Determine the target privilege level corresponding to the first type of exception from multiple privilege levels of the privileged state of the main logical core;

Switch the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core.
The apparatus of claim 13, wherein the processor switches the execution state of the process from the user state of the main logical core to the target privilege level of the privileged state of the main logical core. Previously, also used for:

Obtain the virtual memory address corresponding to the target privilege level;

It is determined that the virtual memory address does not establish a mapping relationship with the physical memory address.
The apparatus according to any one of claims 10 to 12, wherein the first condition includes the process receiving an interrupt, or the process triggering a RAS exception.
The device according to any one of claims 10 to 15, wherein the processor is further configured to:

Start the process in the main logical core;

If the instruction set of the process belongs to the instruction set running from the slave logical core, record the starting position of the process and trigger the slave logical core to enter the running state;

In the slave logical core, the process is run starting from the starting position.
The device according to any one of claims 10 to 16, wherein the processor is further configured to:

Release the hardware resources of the physical core occupied by the main logical core when running the process;

Wherein, the hardware resources include memory resources and/or input and output resources.
The device according to any one of claims 10 to 17, wherein the processor is further configured to:

One or more of the following information is recorded through the slave logic core:

The reason why the process is suspended on the slave logical core, the execution parameters corresponding to the target operation, the environment information when the process is suspended, or privilege level information; wherein the privilege level information is used to indicate The privilege level of the privileged state of the main logical core when the process performs the target operation.
A computer program product, characterized in that the computer program product includes a computer program or instructions, and when the computer program or instructions are executed by a device, the method according to any one of claims 1 to 9 is implemented.
A computer-readable storage medium, characterized in that a computer program or instructions are stored in the computer-readable storage medium. When the computer program or instructions are executed by a computing device, any one of claims 1 to 9 is implemented. method described in the item.
A computing device, characterized in that it includes a processor, the processor is connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the calculation The device performs the method according to any one of claims 1 to 9.