JPS6114736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power factor relay for turning on and off a phase advancing capacitor according to the power factor of a line.

In order to improve the power factor of power receiving equipment, it has been conventional practice to install a power factor improving phase advance capacitor on the power receiving side. In the old system, this capacitor was only installed permanently, and turning the capacitor on and off according to the power factor of the line was rarely done except in large power equipment. For this reason, the phase advance capacitor remains connected to the circuit even during light loads, so at midnight, etc., the total reactance of the phase advance capacitor on the distribution line exceeds the negligible range, causing the line current to advance in phase.
As a result, the line voltage increases and puts stress on the equipment, which is undesirable in the long run because it shortens the life of the electrical equipment connected to the line.

For this reason, automatic power factor adjustment relays have recently come into use, which automatically turn on and off a power factor correction capacitor depending on the power factor of the load. The simplest of these is one in which the capacitor is turned on and off according to the line current, but a slightly more complicated one is one in which the capacitor is turned on and off according to the reactive power, as shown in FIG. That is, the first
In the figure, a line current is introduced by an instrument alternator 1, and a line voltage is introduced by an instrument transformer 2, from which a reactive power detection circuit 3 detects reactive power on the line. Then, the lead/lag determining circuit 4 determines the detected reactive power at a predetermined setting level, and the detected reactive power is classified into three types: a delayed side, a leading side, or a dead zone that is neither of the above. In the case of either the delay side or the advance side, the next stage timer circuit 5 is started, and when a predetermined timer setting time has elapsed, the pulse generation circuit 6 is started and generates step pulses at predetermined intervals. Then, the sequential circuit 7 is driven, and the output circuit 8 outputs a capacitor input signal in the case of a delay side and a capacitor cutoff signal in the case of a lead side in a predetermined sequence. In this way, when the phase advance capacitor is turned on or off and the detected reactive power enters the dead band, the capacitor on/off signal is frozen in order to maintain the capacitor on/off as it is. Then, when the load fluctuates and the reactive power changes and deviates from the dead band, the capacitor on/off signal is output again in the same manner as above.

By the way, in the conventional power factor relay shown in FIG. 1, it is necessary to select one having an appropriate reactive power setting range according to various amounts of power. However, if one power factor relay is to cover a wide range of reactive power, it must have a wide setting range, which proves difficult to manufacture. If the range is divided into different models depending on the setting range, the number of models will increase, which is not desirable in terms of production. In either case, power factor relays end up being expensive.

Furthermore, if power factor improvement is carried out at the terminal load stage, power transmission loss from the power receiving point to the terminal can be reduced, so it is generally considered effective, but if the capital investment for this purpose greatly exceeds the power loss, there is no desire to invest. Does not occur. Therefore, an economical and practical power factor relay is required.

The present invention was developed in view of the above, and by directly detecting the power factor, it is possible to cover the entire power range with one power factor relay, and the circuit configuration is simple. The purpose is to provide a power factor relay that can be realized at low cost.

An embodiment of the present invention will be described below with reference to FIG. In Fig. 2, 10 is the current transformer 1
It shapes the waveform of the line current detected by
It is composed of an inverting amplifier 11 and a NAND circuit 12. The line voltage detected by transformer 2 is
Waveform shaping circuit 2 composed of NAND circuit 21
The waveform is shaped by 0. Waveform shaping circuit 10,
Both outputs of 20 are sent to a phase comparison circuit 30. This phase comparison circuit 30 includes an exclusive OR circuit 31,
The smoothing circuit includes a resistor 32 and a capacitor 33, and generates a DC level output corresponding to the detected phase difference between the line voltage and line current. Furthermore, the detected line current is processed by a level discrimination circuit 41, a smoothing circuit including a capacitor 44,
The current is guided to a current level detection circuit 40 composed of NAND circuits 42 and 43. If this current level is larger than the setting level, the output of the current level detection circuit 40 is "H", and if it is smaller, it becomes "L". The output of the phase comparison circuit 30 is sent to two level discrimination circuits 51 and 52. When the output of the phase comparison circuit 30 is greater than the reference level V _L , the output of the level discrimination circuit 51 becomes "L", and when it is smaller, it becomes "H". Further, when the output of the phase comparison circuit 30 is higher than the reference level V _H , the level discrimination circuit 52
The output becomes "L" and becomes "H" when it is small. These two reference levels V _L and V _H are set to satisfy the relationship V _L <V _H. The outputs of both level discrimination circuits 51 and 52 are each outputted to a NOR circuit 53.
and is sent to the NAND circuit 54. The output of the current level detection circuit 40 is sent to the NOR circuit 53 and the NAND circuit 54. and
The output of the NOR circuit 53 is sent to the output circuit 81 via the timer circuit 71, and the output of the NAND circuit 54 is sent to the timer circuit 72 via the NOR circuit 55 functioning as an inverter, and further sent to the output circuit 82. 99 is a power supply circuit.

The level discrimination circuit 51 detects the lagging side of the phase, and the level discrimination circuit 52 detects the leading side of the phase. Therefore, between the output of the current level detection circuit 40 and the NOR circuit 53
By setting a logic condition in the NAND circuit 54, the output circuit 82 outputs a capacitor when either the power factor is on the leading side or the line current level has not reached the detection level and the load is light. When the power factor is on the lagging side and the line current is large, the output circuit 81 outputs a capacitor closing signal, and when the power factor is on the dead band, neither on the leading side nor on the lagging side, the output circuit 81, 82 can be left as is. Therefore, characteristics as shown in FIG. 3A can be obtained. In FIG. 3A (and also B), the area A is a dead zone, B is the area where the capacitor cutoff signal is generated, and C is the area where the capacitor ON signal is generated. Further, as shown in FIG. 3B, it is also possible to change the center of the power factor range of the dead zone and also change its width.

As described above with respect to the embodiments, according to the present invention, one line current of one phase of the three-phase current is detected, one line voltage corresponding to this line current is detected, and these detected currents and voltages are detected. a first level detection circuit that detects that the power factor exceeds a predetermined value on the leading side by the output of this phase comparison circuit; A second level detection circuit that detects that a predetermined value has been exceeded on the delayed side, a third level detection circuit that detects the level of line current, and the outputs of these first, second, and third level detection circuits. Since it is equipped with an OR circuit and an AND circuit that input the power factor, it is possible to send a capacitor cutoff signal either when the power factor exceeds a predetermined value on the leading side or when the line current does not reach the detection level. Generate a capacitor closing signal when the power factor exceeds a predetermined value on the lagging side and the line current exceeds the detection level, and when the power factor does not exceed a predetermined value on the leading side but on the lagging side. A single power factor relay can operate in all power ranges on the leading side, lagging side, and in the dead band, where the dead band does not exceed the specified value. Since the circuit can be easily constructed, the cost can be very low. Moreover, since it has a current level detection function, it is practical even for terminal loads.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIGS. 3A and 3B are vector diagrams showing characteristics of the power factor relay shown in FIG. 1...Instrument alternator, 2...Instrument transformer, 3
...Reactive power detection circuit, 4... Lead/lag judgment circuit, 5, 71, 72... Timer circuit, 6... Pulse generation circuit, 7... Sequential circuit, 8, 81, 82...
...Output circuit, 9,90...Power supply circuit, 10,20
... Waveform shaping circuit, 30 ... Phase comparison circuit, 40
... Current level detection circuit, 51, 52 ... Level discrimination circuit.

Claims (1)

[Claims] 1 Detect the line current of one phase of the three-phase current and detect one line voltage corresponding to this line current,
A phase comparison circuit that compares the phases of these detected currents and voltages detects that the power factor exceeds a predetermined value on the leading side by comparing the output level of the phase comparison circuit and the first reference voltage. a second level detection circuit that detects that the power factor exceeds a predetermined value on the lagging side by comparing the output level of the phase comparison circuit with a second reference voltage; , a third level detection circuit that detects the level of the detected current; the output from the first level detection circuit and the output of the third level detection circuit are input, and the power factor is set to a predetermined value on the leading side. an OR circuit that ORs an output indicating that the line current has exceeded the detection level and an output indicating that the line current has not reached the detection level;
A first timer circuit into which the output of this OR circuit is input, and a first timer circuit connected to this first timer circuit.
The output circuit, the output from the second level detection circuit, and the output from the third level detection circuit are input, and the output indicating that the power factor exceeds a predetermined value on the lagging side and the line current are at the detection level. an AND circuit that takes an AND with an output indicating that the output exceeds , a second timer circuit to which the output of this AND circuit is input, and a second output connected to the second timer circuit. The circuit generates a capacitor cutoff signal from the first output circuit either when the power factor exceeds a predetermined value on the leading side or when the line current does not reach the detection level, and the power factor is generating a capacitor closing signal from the second output circuit when the line current exceeds a predetermined value on the delay side and exceeds a detection level;
If the power factor does not exceed a predetermined value on the leading side or exceeds a predetermined value on the lagging side, the first and second output circuits are left as they are. power factor relay.