JPS61146976U - - Google Patents

Info

Publication number
JPS61146976U
JPS61146976U JP1985029660U JP2966085U JPS61146976U JP S61146976 U JPS61146976 U JP S61146976U JP 1985029660 U JP1985029660 U JP 1985029660U JP 2966085 U JP2966085 U JP 2966085U JP S61146976 U JPS61146976 U JP S61146976U
Authority
JP
Japan
Prior art keywords
electronic component
adhesive
mounting member
view
sectional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985029660U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985029660U priority Critical patent/JPS61146976U/ja
Publication of JPS61146976U publication Critical patent/JPS61146976U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Details Of Resistors (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の電子部品装置の1実施例であ
り、Aは模式的平面図、Bは模式的断面図を示す
、Cは接着剤がかたよつて塗布された場合の模式
的断面図、Dはコレツトによつて密着された場合
の模式的断面図である。第2図は従来の電子部品
装置であり、Aは模式的平面図、Bは模式的断面
図、Cは接着剤がかたよつて塗布された場合の模
式的断面図、Dはコレツトによつて密着された場
合の模式的断面図を示す。 1…電子部品、2…接着剤、3…装着部材、4
…コレツト、5…穴。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電子部品と、該電子部品を接着剤を介して取り
    付ける為の装着部材とを有する電子部品装置にお
    いて、前記装着部材の前記電子部品装着部分に1
    個以上の前記接着剤導出用の穴が形成された事を
    特徴とする電子部品装置。
JP1985029660U 1985-03-04 1985-03-04 Pending JPS61146976U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985029660U JPS61146976U (ja) 1985-03-04 1985-03-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985029660U JPS61146976U (ja) 1985-03-04 1985-03-04

Publications (1)

Publication Number Publication Date
JPS61146976U true JPS61146976U (ja) 1986-09-10

Family

ID=30528672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985029660U Pending JPS61146976U (ja) 1985-03-04 1985-03-04

Country Status (1)

Country Link
JP (1) JPS61146976U (ja)

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