JPS61146031U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing one embodiment of the waveform processing circuit according to the present invention, Fig. 2 is an operation timing diagram of the circuit shown in Fig. 1, and Fig. 3 is an overall circuit configuration diagram to which the circuit of the present invention is applied. , FIG. 4 is an operation timing diagram of the circuit shown in FIG. 3, FIG. 5 is a circuit configuration diagram of a conventional waveform processing circuit, and FIG. 6 is an operation timing diagram of the circuit shown in FIG. 10...Window comparator, R10, R1
1, R12...Resistor, D1, D2...Diode, OP...Operation amplifier, 20...Output holding circuit,
RS...Reset switch.

Claims (1)

[Scope of utility model registration request] a level setting circuit that creates an upper limit level and a lower limit level; an operational amplifier that inputs the upper limit level to a negative input terminal and the lower limit level to a positive input terminal; a level determination circuit that increases the level applied to the positive input terminal of the operational amplifier when the signal level falls outside the range of the upper limit level and lower limit level; and a level determination circuit that increases the level applied to the positive input terminal of the operational amplifier; 1. A waveform processing circuit comprising: an output holding circuit that returns to hold the output state; and a holding release circuit that releases the holding operation of the output holding circuit.