JPS61145797A - Associative storage device - Google Patents

Abstract

PURPOSE:To obtain an associative storage device having a high-speed operation, large capacity and low cost by securing such a constitution where the read signals of each column of a memory means are equal to an OR or AND of contents of memory elements in each column connected to plural row selection lines selected by a plural row decoding means. CONSTITUTION:In a search mode an action mode signal 103 of '0' is supplied together with a write signal 104 of '1'. In addition, the search information divided into N pieces are supplied as N pieces of M-bit input data 101. Each row decoding means 120 drives selectively a row selection line 121 of the row designated by the data 10. A registered row driving means 130 drives the line 121 of the lowest row of a memory means 110. Then the contents of all row memory elements connected to the driven (N+1) pieces of lines 121 are read all at once. The read data lines 211 of each memory element stored in a memory means 110 are internally connected in common for each column. Therefore the read signals given from the memory elements connected to said (N+1) pieces of lines 121 undergo the NOR and are supplied to an output means 150 in the form of read signals 111 of each column.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an associative memory device, that is, a memory device that can perform addressing based on stored contents.

[Prior art and its problems]

This type of associative memory device is an important device used as one of the components of electronic computers.An example of the application of the associative memory device is ``Ultra-high performance electronic computer using large project'' (edited by Agency of Industrial Science and Technology, Ministry of International Trade and Industry). .

PP45 (published by Japan Industrial Technology Promotion Association, July 1947)
According to this, associative memory stores which address of the main memory corresponds to a sector of the buffer memory, and speeds up address conversion from a logical address to a physical address by searching the contents. make it possible to do

In addition, there is a list process on pages 102 to 136 of 1 Nikkei Electronics (published on October 27, 1980).

Applications to image processing and databases are described.O There are already many documents regarding associative memory elements used in this type of associative memory device, such as the ``Information Processing Handbook.''
"Logical Memory" published in May 1947 by Ohm Publishing, edited by Information Processing Society of Japan.

PP13-96-PF13-99), etc. According to this, this type of associative memory device is equipped with a coincidence detection circuit that checks the coincidence between the stored content and the search information for each memory element that can store information. It requires an associative memory element of the provided configuration. Therefore, compared to memory elements used in ordinary memory devices that are accessed by supplying an address indicating the storage location Rt of desired data, conventional associative memory elements have a more complex structure and a higher cost per bit. ◎ In order to eliminate this drawback, an associative memory device that uses a normal memory element in the part that stores information and has a match detection circuit for each word has been considered. However, searching this associative memory device had the drawback of requiring a number of search operations corresponding to the number of bits.

Further, the search information is used as an address input, a first ordinary storage element that stores data information, and the data information or a readout output of the first ordinary storage element is used as an address input;
An associative memory device using a second ordinary memory element for storing search information is disclosed in 1973-73039. However, although this associative memory device has the advantage of being constructed using ordinary memory elements, as the number of bits of search information or data information increases, the number of memory elements required increases significantly, resulting in an increase in price. have.

[Purpose of the invention]

The purpose of the present invention is to provide a high-speed,
The purpose is to provide a large-capacity, low-cost associative memory device.

Another object of the present invention is to provide an associative memory device that is capable of performing a search operation while masking a part of the search information or registered information. An object of the present invention is to provide an associative memory device that enables a search using a data stream with unclear delimiters as search information.

Another object of the present invention is to reduce the cell size and the number of connection lines, and to provide a low-cost content addressable memory element. is obtained. That is, a storage means in which storage elements are arranged in rows and columns, a plurality of row decoding means for supplying write data or read row selection signals based on input data to a plurality of row selection lines of the storage means, and Three-column decoding means supplies a write control signal to a storage element in a column designated by a registered address, and a read signal for each column of the storage means is input.

output means for generating search address information, wherein the read signal of each column of said storage means is the OR of the contents of the storage elements in each column connected to a plurality of row selection lines selected by a plurality of row decoding means; A content addressable memory device which is an AND, a storage means in which storage elements are arranged in matrix, a shift register including a plurality of registers connected in series, and each stage of the shift register is connected to a plurality of row selection lines of the storage means. a plurality of row decoding means for supplying write data or read row selection signals based on the contents of the registers; and column decoding means for supplying write control signals to the storage elements of the columns designated by the registered addresses in the storage means; a plurality of row selection lines, the read multi-signal of each column of the storage means being selected by a plurality of row decoding means; an associative memory device that is the logical sum or logical product of the contents of the storage elements in each column connected to the memory cell; , a column selection line that instructs writing to a memory cell, a write selection transistor that selectively supplies write data on a row selection line to a memory cell via a column selection line, and a row selection line that selects all contents of a memory cell. This is an associative memory device using associative memory elements, characterized in that the outputs of the read select transistors of memory elements in adjacent rows are commonly connected.

〔Example〕

The present invention will be explained in more detail using the following nine pages.

FIG. 1 is an explanatory diagram of an embodiment of the content addressable memory device according to the present invention. This outputs the following. A memory means 110 constituted by memory elements arranged in a matrix, 1M-bit input data 101 and a mask signal 102 are input, and is connected to the memory means 110 by a row selection line 121 to the row decoding means 120 of N(II). , operation mode signal 1
03 as an input and is connected to the storage means 110 through a row selection line 121; and a column decoding means 140 that takes the registration address 142 and write signal IL)4 as input and is connected to the storage means 110 and a column selection line 141. and an output means 150 which inputs read multi-signals 111 i of each column of the storage means 110 in parallel and outputs search address information 152 indicating the column of the storage means in which information matching this is stored to an external device. Prepared and configured.

The memory configuration of this associative memory device is MXNpi)2K")-
When Y and f, the storage means 110 is (2MXN+1) row 2
◎In this case, search information and registration information are stored in M
(XN pits), they are divided into N parts and supplied as input data 101 of N M pits. Further, the number of bits of the registered address 142 is 2 bits.

Next, before explaining the operation of the associative memory device shown in FIG. 1, the operation of the storage means 110 will be explained.

FIG. 2 shows a connection diagram of each storage element within the storage means 110. Each memory element 210 has a row selection line 1212 and a column selection line 141.
, are connected by a read multi-signal line 211. Row selection line 121 for each row, column selection line 141 for each column, and read multi-signal line 2 for each column
11 are commonly connected and taken out to the outside. ◎ A load resistor 220 is connected to the read multi-signal line 211 of each column.
Column selection line 141 allows writing to one column of storage element 210, and write data at this time is supplied via row selection line 121. That is, writing is done in parallel to specific columns. The row selection line 121 is also used to instruct reading of the storage contents of the storage elements 210 in each row. The contents of the storage elements of the plural rows designated to be read from the row selection line 121 are transferred to the wired N by the commonly connected read signal +11211.
It is OH'd and output. - As an example, the contents of the storage elements in any column of the three specified rows are read as A, B, and C.
Then, the logic of A+B+C is performed by the load resistor 220 and the read multi-signal line 211, and the read multi-signal edge 21
1 is output. That is, by the NOR, a read multi-signal 111 of 11'' is generated on the read signal line 211 when the contents of the storage elements instructed to be read are all @O'.

The operation mode of the associative memory device in FIG. 1 is the operation mode signal 1.
03 and write signal 104. As a combination of these signals (0,1) v (0,0).

When (1, 0) is supplied, a search operation, a registration operation, and a deletion operation are performed, respectively. As explained earlier, the row selection line 121 of the storage means 110 is connected to the storage means 1 during the search operation.
It serves as a row selection line for a read operation into the storage elements of each row of 10, and serves as a data line for each row during a registration operation and a deletion operation.

During the registration operation, each row decoding means 120 decodes the input data 101 ft, which is partial data of the registration information, and supplies it to each row selection line 121. Further, the column decoding means 14
0 by the write signal of 10''), selects the select line 141 specified by the registration address 142, and allows parallel writing of the write data indicated by row select &121 to that column.The registration information is N. M-bit input data 101
Since the column designated by the registered address 142 of the storage means 110 is divided into 10" write data and supplied to each row decoding means 120, only the row designated by each input data 101 has an opening or , write data @0'' is supplied to the row selection line 121 of the lowest row of the storage means 110 by the registered row driving means 130. Therefore, 10' indicating that it has been registered is stored in the storage element of the column specified by the registration address 142 of the lowest row.

During deletion operation, 11" operation mode signal 103 and @0'
registration row driving means 13, which is supplied with a write signal 104 and a registration address 142 indicating the column to be deleted;
When the operation mode signal 103 of 0 is @l'' is supplied, write data of @1'' is supplied to the row selection line 121 of the lowest row. Therefore, @1' indicates that the memory element in the column specified by the registration address 142 in the lowest row is not registered.
is stored and a deletion operation is performed.

During search operation, @0″ operation mode signal 103 and @l”
The write signal 104 is supplied, and the search information divided into N is supplied as N pieces of M-bit input data 101.
The registered row driving means 130 selectively drives the row selection line 121 of the row specified by i, and the registered row driving means 130 drives the row selection line 121 of the lowest row of the storage means 110.
1) Row selection line 121 The contents of the storage elements in all connected columns are read at once. The data lines 211 for reading each storage element in the storage means 110 are internally connected in common for each column. Therefore, the read signals from the storage elements connected to the driven (N+1) row selection lines 121 are NOR'd within each column, and the read signals 111 of each column are
The signal is supplied to the output means 150 as a signal.

The registration information is divided into N pieces of input data 101.

Since only the row specified by each input data 101 is stored with a bit bang of 101, the contents of the selected (N+1) storage elements of the column in which registered information matching the search information is stored are negated. Read multiple signal 1 which is the logical sum result
11 becomes 11'. Furthermore, in a column where registration information that differs from the search information by even one bit is stored, the read multi-signal of the storage element connected to the row selection line 121 specified by the different input data 101 becomes 11'. Therefore, the read signal 111, which is the NOR result of the contents of the storage elements specified by each input data 101, becomes @O. Since the reading signal 111 of the storage element in the row is also included, the reading signal 111 of the deleted column is always 10''. In other words, the reading signal 111 of each column is stored in each column of the storage means. 11" and @0" indicate whether the registered information and the given search information match, respectively.

The mask signal 102 input to each row decoder means 120 is a mask signal 1 of "o@0" which is used for the search by masking the input data unit of search information t-M bits.
02 is supplied and the round decoder 120 supplies @1'' to all the row selection lines 121 connected to it, so reading of the memory element connected to that row selection line 121 is prohibited.
Therefore, it is possible to mask the search information in units of M bits.

This read signal 111 is supplied to the output means 150.
The output means 150 is a buffer amplifier for supplying the read multi-signal 111 as search address information 152 to external equipment, and a parallel input serial output shift register that inputs the read signal 111 in parallel and outputs it in series as search address information 152. Ya reading! ◎If a shift register or encoder is used as the output means 150, the number of bits of the search address information 152 will be small, and the number of input/output terminals will be reduced. be done.

As explained above, this associative memory device is (2MXN+
1) By using memory elements in rows and columns, it is possible to construct a word content addressable memory device of 1 MXN bits. - As an example, M=
2, N=64, K=12 (128 bits in l mechanical pit memory element) 4096 words, i.e. 5
An inexpensive associative memory device with a large capacity of 12 kilobits can be realized. Also, it is possible to perform a search by masking part of the search information. Additionally, exploratory behavior.

The deletion operation and the registration operation are performed by accessing the storage means 110 once, and the operations are extremely fast compared to conventional bit serial or word serial content addressable memory devices. The information indicating the usage status of the column is stored in the storage element of the lowest row, but if the mask signal 102 is supplied to each row decoding means 120 during the deletion operation, the contents of the storage element of the column specified by the registered address 142 can be stored. All data can be written to @1'm, leaving that column unused. Therefore, it is also possible to omit the lowest row of the storage means 110 and the registration drive means 130. FIG. This is an explanatory diagram of one embodiment of a memory element constituting the memory means of FIG. 2. ◎This memory element has Qs vQs =
Qi - Qt P channel MO8) transistor and Qz
-Qa -Qa N-channel MO8) transistor Qs e Qt yQs composed of transistors
= Qa Kyo Kuko/Primen fisu Mos (0MO
To write to a 0 memory cell in which the memory cell 8) is configured and to which a power supply voltage VDD and a lower substrate voltage v0 are applied, a voltage v is applied to the column selection line 141 and an honor signal is written to the 1st row selection line 121. Included data @1”.

- This is done by supplying the voltage VDD I VBTU corresponding to @01. That is, transistor Q5
When voltage Vglt- is applied to the gate of transistor Q
5, and a voltage corresponding to the write data on the row selection line 121 is supplied to the gate of the transistor Q39Qa. When the transistor Q4t Ql becomes conductive, the transistor Q3t Q2 becomes open, and data @1'' is stored in the memory cell. When voltage vl is applied to row selection line 121, transistor Q4#Ql is opened and transistor Q3*Q2
becomes conductive, and data @O'' is stored in the memory cell ◎ Therefore, the contents of the memory cell @llll, @Q'' are the transistor Q
3 corresponds to the gate voltage vall m vDI).

The contents of the memory cell are determined by applying the voltage Vast to the row select line 121. In this case, transistor Q7 is conductive and transistor Q6 is conductive when the memory content is @1'' and open when the memory content is 99m. Therefore, an inverter is configured by the load resistor 220 shown in FIG. 2 connected to the read multi-signal line 211 and the transistors Q6 and Q7.As shown in FIG. Since it is connected, the load resistance 22
0 and transistor Q6 in the plurality of storage elements. A j5 NOR gate is configured by Q7. Therefore, the contents of the storage elements 210 that are commonly connected by the read (read) signal line 211 and to which the voltage V□ is applied to the row selection line 121 are all ``0''. Only in this case, the voltage of the read multi-signal line 211 becomes VDD. That is, a read multiple signal ill of @1'' is generated. This storage element has the same number of connection lines as the CMO8 static 85M which is accessed by supplying a normal address, but has only one more transistor. Therefore, compared to conventional content addressable memory elements, the number of connection lines and transistors is small, resulting in a reduction in price.

FIG. 4 is an explanatory diagram of another embodiment of the memory element.

This storage element is a bipolar PROM, and a fuse 420 is provided between the emitter of the transistor 410 and the read signal line 211. The memory content @Om is made to correspond to the blowing of the fuse by supplying the power supply voltage VDD″f to the row selection line 121.

The logical sum of the contents of the selected storage elements is output to the read multi-signal line 211 which is commonly connected to the plurality of storage elements. Therefore, the read signal Ill of 10 m is generated on the read multi-signal line 211 only when the contents of the selected 9 memory elements are all @Om.The content addressable memory device using this memory element does not allow rewriting of registered information. However, since it is possible to realize a storage means 110 with a larger capacity than the storage element shown in FIG. 3, it is suitable for applications such as language translation dictionaries that do not require rewriting.

FIG. 5 is an explanatory diagram of an embodiment of an associative memory device according to another invention. This associative memory device inputs a long data stream as search information and checks where data matching the registered information is contained in the input data stream, as shown in Figure 1. 0 shift register 52 which is an associative memory device and includes a corresponding associative memory unit 510 and a shift register 520 that converts a serially input data stream into parallel and supplies input data 101 to the associative memory unit 510.
0 consists of registers 530 connected in series.

Search information data system) 9 - The search information and registration information are input as 5 M-bit partial data 501 t in series in synchronization with the black signal 531.The search information and registration information are input in parallel with JXM bits. 8 OJXM bits input to
Bits are input in symbol units expressed in ASCII code, etc., and are convenient for matching symbol strings. in this case,
In FIG. 5, J=4°M=2, and the number of bits of the partial data 501 and the input data 101 to the associative memory unit 510 is 2 bits.◎ In the registration operation, the partial data 501 is stored in the shift register 520.
Registration information is input in synchronization with the clock signal 531 in units, and when this is completed, the registration information from each register 530 is supplied in parallel to the content addressable memory unit 510 as input data 101. The operation mode signal 103 and the write signal 104 of @0' are supplied, and the content addressable memory 2nit-N is supplied in the same manner as the content addressable memory device shown in FIG.
A registration operation is performed. Deletion operation is performed using operation mode signal 10.
By replacing 3 with @1', the same operation as the registration operation can be performed. However, it is not necessary to input registration information.0 In the search operation, the partial data 501 is stored in the shift register 520.
Search information is input sequentially in synchronization with the clock signal 531, and each register 5 is input every time partial data 501 is input.
The search operation in the associative memory unit 510, which uses the oral input data 101 as the search information, which supplies the input data 101 from 30 in parallel to the associative memory unit 510 as search information, is performed in the same way as the associative memory device shown in FIG. Search address information 152 indicating the address where registered information matching the information is stored is output. This associative memory unit 5
The search operation in step 10 uses partial data 501t as search information.
-It is done every time it is done manually. Therefore, the search information is JXM
If the oJxM bit in which a search operation is performed while shifting bits indicates one symbol, symbol string matching can be performed while sequentially shifting symbols.

Note that the mask information 502 is used to mask part of the search information, moves together with the search information within the shift register 520, and is supplied to the associative memory unit 510 as the mask signal 102. A search operation with part of the registered information masked is possible by directly supplying the mask signal 102 from the outside.

This associative memory device stores search information and registration information as partial data 5.
Since each 01 is input serially, the number of input terminals can be reduced.In addition, a data stream with unclear boundaries between pieces of information can be handled as search information, making it possible to match symbol strings within a long symbol string. do.

〔Effect of the invention〕

As explained above, the associative memory device according to the present invention is an inexpensive storage means 110 that uses memory elements of approximately the same cell size as a normal memory confectionery, which is accessed by supplying an address indicating the storage location of desired data. Can be configured
(2MXN+1) A low-cost, large-capacity associative memory device with MXN bits per word can be constructed by using a memory element with 2 bits per word. Therefore, if we use l mechanical pit semiconductor technology, - for example, M=2. If N=32, an 8 kiloword, 64 bit, or 512 kilobit content addressable memory device can be realized with one chip. Compared to the capacity of commonly available semiconductor associative memories, which are less than 1 kilobit, the storage capacity of the associative memory device according to the present invention can be said to be extremely large. The search operation and registration operation of this content addressable memory device can be completed with one access to the storage means 110, which is faster than conventional word serial/bit parallel or word parallel/bit serial content addressable memory devices.

Furthermore, it is also possible to perform a search operation by masking part of the search information. In addition, a data stream with unclear boundaries between pieces of information is input sequentially as search information.

It is also possible to perform a search operation by moving the search information.

Therefore, if the search information or registration information is a t-signal sequence.

This enables symbol string matching, which is necessary for language translation, text searches, etc. Using the l-mecha-bit semiconductor technology shown above, it is possible to store 8 symbol strings of length t - 8,000 on a l chip, and to collate 8,000 words per l chip at an extremely low cost, high speed, and small size. In addition, the memory element shown as an example in Fig. 3 has a significantly reduced number of transistors and connection lines compared to a conventional content addressable memory element, and has a smaller cell size. can be reduced. Also, the fourth
The memory element shown as an example in the figure is composed of one transistor, and the cell size can be further reduced, making it possible to realize a content addressable memory device with a much lower cost and larger capacity.

Further, this associative memory device performs an AND operation of read multi-signals of a plurality of storage elements on a read multi-signal line 211.

If the storage means 110 is separated for each row decoding means 120 and the AND operation of the read multiple signals is performed outside the storage means, the area for the signal line leading the read multiple signals to the AND means provided outside the storage means is significantly increased. - For example, even if you use a storage means with 8,000 columns and read multi-signal lines from each column and wire them at a pitch of t-2 microns, a 2-mm sub-wiring area is required for 1,000 wires. . However, since the associative memory device of the present invention performs logical product on the read multi-signal line 211, it does not require a special wiring area for logical product. The memory element shown in FIG. 4 is an example;
Other static memory devices, IPROMs, etc. can be used as well, and the above description does not limit the scope of the claims of the present invention.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of an associative memory device according to the present invention, FIG. 2 is an explanatory diagram of an embodiment of the storage means used in FIG. 1, and FIGS. 3 and 4 are associative memory devices according to the present invention. FIG. 5 is an explanatory diagram of an embodiment of a memory element, and FIG. 5 is an explanatory diagram of an embodiment of an associative memory device according to the second invention. 110...Storage means, 120...Line decoding means,
130... Registration row driving means, 140... Column decoding means, 15G... Output means, 210... Memory element, 220... Load resistance, 420... Hiace, 51
0... Content addressable memory unit, 52°... Shift register, 53o... Register. Tei 1 l Tei 2 side Q2. Q4. Q6 ---N Nayasoru MO5? Ranjinuta OO Hughes 420

Claims (3)

[Claims] (1) A storage means in which storage elements are arranged in rows and columns; a plurality of row decoding means for supplying write data or read row selection signals based on input data to a plurality of row selection lines of the storage means; The storage means comprises a column decoding means for supplying a write control signal to a storage element in a column specified by a registered address, and an output means for inputting a read signal for each column of the storage means and generating search address information. A content addressable memory device characterized in that the read signal for each column is the logical sum or logical product of the contents of storage elements in each column connected to a plurality of row selection lines selected by a plurality of row decoding means. (2) A storage means in which storage elements are arranged in a matrix, a shift register including a plurality of registers connected in series, and writing to a plurality of row selection lines of the storage means based on the contents of registers in each stage of the shift register. a plurality of row decoding means for supplying data or read row selection signals; column decoding means for supplying write control signals to the storage elements of the columns specified by registered addresses in the storage means; and readout of each column of the storage means. output means for receiving a signal and generating search address information, the read signal of each column of the storage means being connected to a plurality of row selection lines selected by a plurality of row decoding means of storage elements in each column; An associative memory device characterized by a logical sum or logical product of contents. (3) A memory cell that stores information, a row selection line that shares write data and read instructions to the memory cell, a column selection line that instructs writing to the memory cell, and a column selection line that writes data on the row selection line. A write selection transistor selectively supplies data to storage cells through a selection line, a read selection transistor that selectively outputs the contents of a storage cell through a row selection line, and a read signal detection line. 1. An associative memory device comprising an associative memory element in which the output of a read selection transistor is connected to the common read signal detection line.