JPS61145657A - History memory control circuit - Google Patents

Abstract

PURPOSE:To attain ease of analysis of a history data by providing a counter addressing a history memory, its backup register, a comparator circuit detecting a transition point and a control circuit for load/restorage of counter content. CONSTITUTION:Contents of the 1st and 2nd registers 5, 6 are fed to a comparator circuit 7 to check coincidence/dissidence. A comparison result signal is fed to a control circuit 8 to attain control condition of the counter 2. When there is a change in a time series data read in ascending order from a history memory 1, the transition point is detected by the detection of dissidence by the circuit 7. When the dissidence is detected by the circuit 7, the control circuit 8 controls to stop the counter 2. The content of the stopped counter 2 is an address representing the transition point of the time series data. The 1st register 5 is used as a service processor (SVP) interface register and the content of the register 5 is fed to the SVP.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention enables hack tracing of history data collected in a history memory control circuit, particularly in a history memory mechanism, by dividing transition points of one time series data, and easily performs hack tracing. This invention relates to a history memory control circuit that can analyze history data.

[Conventional technology and problems]

History memory is a memory provided in a computer system for debugging, etc., and stores internal state data related to the computer system, such as specific registers, in sequence.
This is a memory that records data in chronological order. By analyzing the history data stored in the history memory, the operation history of the computer can be grasped, and when an abnormality occurs, the cause can be investigated. Normally, when analyzing historical data, a bank trace is often used to track changes in data in reverse order over the course of one hour.

In the conventional history memory mechanism, when taking a backtrace of history data, for example, a service processor (S
Historical data was analyzed by loading the history data into the memory on the VP) and processing it with a program running on the SVP. Therefore, according to the conventional method, sufficient memory is required as a resource to store the loaded history data.

Another problem is that all procedures for processing data must be prepared on the svp.

Means for Solving Problem C] The present invention aims to solve the above problems, and in order to facilitate the analysis of history data collected in the history memory, an efficient method is provided in which transition points of one time series data are separated. Provides a means to perform bank tracing.

Therefore, the history memory control circuit of the present invention is as follows.

A history memory control circuit that controls a history memory that records data related to an internal state in a computer system in time series, comprising: a counter that addresses the history memory; a back amplifier register that stores the contents of the counter; and the counter in the history memory. and a control circuit that controls the operation of the counter and the loading/restoration of the contents of the counter to the backup register. There is. Embodiments will be described below with reference to five drawings.

〔Example〕

The figure shows a block diagram of an embodiment of the present invention.

In the figure, 1 is a history memory where history data is recorded in chronological order, 2 is a counter that addresses history memory l, 3 is a backup register that saves the contents of counter 2, 4 is a selector, and 5 is from history memory l. A second register 6 stores the read data, and a second register 6 stores the contents of the register 5 with a delay of one cycle.

7 is a comparison circuit that compares the contents of the second register 6 with the contents of the second register 6; and 8 is a control circuit that outputs a control signal that controls the operation of the counter 2 and a bank-up register control signal that controls the backup register 3. represent.

When the computer system provided with the history memory 1 operates and history data is collected.

The counter 2 is a service processor (SV) (not shown).
The inverted signal from P) and the counter control signal from the control circuit 8 are used to sequentially perform count amplification. The history data obtained from a specific register or the like is sequentially recorded in nine time series at the address pointed to by the counter 2. At this time, when the contents of the counter 2 are updated, the contents of the counter 2 are saved in the bank-up register 3 in response to a backup register control signal from the control circuit 8. That is, the backup register 3 is designed to hold the final address at the time of history data collection.

After collecting the history data, when analyzing the history data by bank trace, read the noteworthy history data to the register 5, and input a signal obtained by switching the inverted signal ON10 F F from svp to start the back trace. . In response to this inverted signal, the control circuit 8 outputs a bank amplifier register control signal that inhibits writing to the bank up register 3. Further, based on this inverted signal, the counter 2 thereafter attrends the history memory 1 while sequentially counting down. In synchronization with this, the first time series data is transferred from the fifth Lujista to the second
Transition to register 6.

Time series data that goes back one period is newly read into the register 5 from the history memory 1.

The contents of the first register 5 and the contents of the second register 6 are supplied to a comparator circuit 7.

Match/mismatch is checked. A signal resulting from the comparison is supplied to the control circuit 8 and is used as a control condition for the counter 2. When there is a change in the time-series data sequentially read back from the history memory 1, the point of change is detected by the comparison circuit 7 detecting a mismatch. Control circuit 8
controls the counter 2 to stop when a mismatch is detected in the comparison circuit 7. The contents of the stopped counter 2 become an address indicating a transition point of one time series data. In addition, the 5th Lujista.

It is also used as an SVP interface register, and the contents of register 5 are supplied to SVP.

When history data collection is resumed from the interrupted point, the 9 inverted signal is returned to its original state, and the contents of the bank up register 3 are transferred to the counter 2 via the selector 4. This makes it possible to sequentially record the primary history data starting from the last address at the time of previous history data collection. Also, via the selector 4,
By setting address data to the counter 2, data can be recorded or read from a new address.

Furthermore, in one circuit, by converting the 9 inversion signals to 0N10FF, it is possible to perform tracing using transition points of time-series data as delimiters in either the sequential direction or the sequential direction.

〔Effect of the invention〕

As explained above, 1. According to the present invention, when analyzing historical data, it becomes possible to easily trace noteworthy time-series data using transition points as delimiters. 2. For example, the memory of a service processor , it becomes possible to significantly reduce the burden on programs that process historical data. Particularly when analyzing historical data that changes over a long period of time, it is efficient because it is possible to automatically detect points that change by one using pack tracing.

[Brief explanation of drawings]

The figure shows a block diagram of an embodiment of the present invention. In the figure, 1 is the history memory, 2 is the counter, 3 is the backup register, 4 is the selector, 5 is the second register, 6
is the second register, and 7 is the comparison circuit. 8 represents a control circuit.

Claims (1)

[Claims] A history memory control circuit that controls a history memory that records data related to an internal state in a computer system in time series includes a counter that addresses the history memory, a backup register that stores the contents of the counter, and the counter in the history memory. The present invention is characterized by comprising a comparison circuit that detects a transition point regarding the time series data read from the indicated address, and a control circuit that controls the operation of the counter and the loading/restoration of the contents of the counter to the backup register. History memory control circuit.