JPS6114525B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a position control circuit in a numerical control device that controls machine tools and the like. FIG. 1 is a block diagram showing the configuration of a numerical control system. In the figure, 1 is a command table. For example, when cutting, first from the drawing of the workpiece to be cut,
First, obtain the numerical information necessary for machining, such as numerical values regarding dimensions and feed rate. A command tape is a tape made by punching this numerical information according to certain rules. 2
is an information processing circuit that converts information recorded on the command tape 1 into a command pulse train. 3 is a position control circuit which outputs a control output to the motor and controls the rotation direction and rotation speed of the motor. Reference numeral 4 is the motor, and as the motor 4 rotates, the cutting tool 5 moves. 6,7
is a gear, and 8 is a feed screw. Although the figure only shows the motor that controls the bite position in the X direction, a motor with a similar configuration that controls the bite position value in the Y direction is also provided. A synchro resolver (bit position detector) 9 has a rotating body that rotates in conjunction with the rotation of the main shaft of the motor 4, and outputs an output signal having a phase corresponding to the rotation angle of the rotating body. This output signal is fed back to the position control circuit 3. The position control circuit 3 detects the phase difference between the control output signal phase-modulated by the command pulse output from the information processing circuit 2 and the output signal output from the synchro resolver (hereinafter simply referred to as resolver). , outputs to the motor 4 a DC voltage corresponding to the sign and magnitude of this phase difference. This controls the rotational direction and rotational speed of the motor 4. This control is performed until the phase difference between the control output signal and the resolver output signal becomes zero, and the movement of the cutting tool 5 is completed. However, such numerical control devices have the following drawbacks. That is, it can only be used when the phase difference between the control output signal and the resolver output signal changes within a range of ±180°, and the position control range is limited. By suppressing the feeding speed of the cutting tool, that is, by setting the output frequency of the command pulse low, it is possible to set the phase difference between the two signals so that it is always within the range of ±180°. However, when it is required to increase the feeding speed of the cutting tool, the phase difference between the two signals exceeds the range of ±180°, making it impossible to control with a conventional numerical control device. For example, when dry-feeding a cutting tool, it is more efficient to increase the feed rate as much as possible, but if the feed rate is increased, the phase difference between the control output boost and the resolver output signal will be within a range of ±180°. It was impossible to control with conventional numerical control equipment. The present invention has been made in view of this point,
Even if the phase difference between the two signals exceeds the range of ±180°, a numerical control device that can correctly output a DC voltage proportional to the phase difference and control a machine tool, etc. More specifically, a numerical control device This was developed with the aim of obtaining a position control circuit that would The present invention will be described in detail below based on Examples. FIG. 2 is a block circuit diagram showing a position control circuit which is an embodiment of the present invention. In the figure, 10 is a counter circuit that outputs the control output signal. When no command pulse is applied, a constant frequency reference clock pulse is input to the counter circuit 10.
CP is given and this reference clock pulse
The counter circuit 10 outputs a rectangular wave (4 KHz rectangular wave in this embodiment) that repeats "1" and "0" every CP100 pulse. This signal is called a reference signal. When a command pulse is applied, for example, when one command pulse of 10 is applied, one clock pulse is supplied to the counter circuit 10 in addition to the reference clock pulse CP. As a result, the counter circuit 10
The output signal (control output signal) is clock pulse 1
The phase advances by the amount corresponding to the number. Conversely, when one command pulse is applied, one of the reference clock pulses CP is thinned out. As a result, the output signal of the counter circuit 10 is delayed in phase by an amount corresponding to one clock pulse. Ten or one command pulses are supplied at a constant frequency (proportional to the feed rate of the cutting tool), and based on this, the counter circuit 10 outputs a control output signal that is phase modulated as described above. This control output signal A is supplied to a resolver (not shown).
It is input to the phase difference positive/negative detection circuit 11 together with the output signal B of . A phase difference positive/negative detection circuit 11 detects whether the phase difference between the two signals is positive or negative. To be precise, the signal input to the phase difference positive/negative detection circuit 11 is not the control output signal A, but a special signal created based on the control output signal A.
Details will be described later. The sign of the phase difference is defined as shown in FIG. In other words, the resolver output signal B is higher than the control output signal A.
If the phase is ahead of the other, the phase difference is positive, and if the opposite is the case, the phase difference is negative. 12, the magnitude (absolute value) of the phase difference between the control output signal A and the resolver output signal B is (360×n)°-
Is it within the range of (360×n+180)°?
This is a phase difference detection circuit that detects whether the phase difference is within the range of +180)°-(360×n+360)°. n is 0 or a positive integer. Hereinafter, the magnitude of the phase difference refers to the absolute value, ignoring whether it is positive or negative. The phase difference detection circuit 12 receives the control output signal A, the resolver output signal B, and the phase difference positive/negative detection circuit 11.
The range of the phase difference is detected based on the output of the phase difference. The principle of the phase difference detection circuit 12 will be explained based on FIG. 4. That is, the position is determined based on whether the control output signal A is at "1" or "0" when the resolver output signal B falls, and whether the output of the phase difference positive/negative detection circuit 11 is a positive output or a negative output. Detect the range of phase difference size. [When the output of the phase difference positive/negative detection circuit 11 is a positive output] If the signal A is “1” at the falling edge of the signal B, the magnitude of the phase difference is (360×n)゜−(360×n+
180)°, and if it is “0” then (360×n
+180)° - (360×n+360)° and outputs it. [When the output of the phase difference positive/negative detection circuit 11 is a negative output] If the signal A is “0” at the falling edge of the signal B, the magnitude of the phase difference is (360×n)゜−(360×n+
180)°, and if it is “1”, it is (360×n
+180)° - (360×n+360)° and outputs it. 13 is an exclusive OR circuit which receives the control output signal A and the resolver output signal B as its two inputs. Furthermore, 14 is a first filter circuit that outputs a DC voltage proportional to the pulse width of the output signal based on the output signal of the exclusive OR circuit 13. 15 is a second filter circuit that outputs a DC voltage proportional to the pulse width of the signal based on the signal obtained by inverting the output signal of the exclusive OR circuit 13 by the inverter 16 (the inverted output signal of the exclusive OR circuit); be. First filter circuit 14, second filter circuit 15
The output voltage waveform of is shown in FIG. (Fig. 8 102
(See also the output waveform of the first filter circuit 14, 103 and the second filter circuit 15) In the figure, the dotted line indicates the output voltage of the first filter circuit 14, and the solid line indicates the second filter circuit 15. is the output voltage of As is clear from the figure, when the magnitude of the phase difference is within the range of (360×n)° - (360×n+180)°, the output voltage of the first filter circuit 14 is equal to the magnitude of the phase difference. When the magnitude of the phase difference is within the range of (360×n+180)°-(360×n+360)°, the output voltage of the second filter circuit 15 increases in proportion to the increase in the magnitude of the phase difference. increases in proportion to Reference numeral 17 denotes a bias voltage output circuit, which is controlled based on the judgment output of the phase difference detection circuit 12. This bias voltage output circuit 17 is a characteristic part of the present invention. That is, with this bias voltage output circuit 17, even if the phase difference between the control output signal A and the resolver output signal B exceeds the range of ±180°, the position control circuit of the present invention generates a DC voltage proportional to the phase difference. can be supplied to the motor and controlled correctly. To explain in more detail, the bias voltage output circuit 17 outputs a signal whose phase difference between the two signals A and B is within the range of (360×m/2)°-(360×m/2+180)° to (360×m/2+180)°. m / 2 + 180) ° - (360 × m / 2 + 360) ° [or when the magnitude of the phase difference changes from within the range of (360 × m / 2 + 180) ° - (360 × m / 2 + 360) ° (360×m/2)°-(360×m/2+180)°], the output bias voltage is increased (or decreased) by a certain amount stepwise. m is 0 or a positive integer. The fixed amount is configured to be equal to the output voltage value of the first filter circuit when the phase difference is 180 degrees, for example. With this configuration, the bias voltage output circuit 17 outputs a bias voltage that increases stepwise as the magnitude of the phase difference increases,
Conversely, as the magnitude of the phase difference decreases, a bias voltage is output that decreases in stages. Output of the filter circuit 14, filter circuit 1
5 and the output of the bias voltage output circuit 17 are input to the analog gate 18.
8, based on the output of the phase difference detection circuit 12, synthesizes and outputs a DC voltage that is correctly proportional to the magnitude of the phase difference from the outputs of the three circuits. In other words, the magnitude of the phase difference is (360×n)゜−(360×
In the range of n+180) degrees, an output voltage that is a combination of the output of the first filter circuit 14 and the output of the bias voltage output circuit 17 is output based on the output of the phase difference detection circuit 12. In addition, when the magnitude of the phase difference is in the range of (360×n+180)°-(360×n+360)°, an output voltage that is a combination of the output of the second filter circuit 15 and the output of the bias voltage output circuit 17 is output. do. (Analog gate 1 in Fig. 8 105
8) 19 is an inverting amplifier with a gain of (-1), and the output of the analog gate 18 is given to the analog gate 20 directly and via the inverting amplifier 19. The analog gate 20 detects the analog gate 18 based on the output of the phase difference positive/negative detection circuit 11.
Either the output of the analog gate 18 or the output via the inverting amplifier 19 of the analog gate 18 is output to the motor drive circuit. That is, the polarity of the DC voltage is controlled based on whether the phase difference is positive or negative. As a result, a DC voltage having a polarity corresponding to the positive or negative phase difference and a magnitude proportional to the magnitude of the phase difference is output to the motor drive circuit, and the DC voltage is outputted to the motor drive circuit, and the DC voltage has a polarity corresponding to the positive or negative phase difference and a magnitude proportional to the magnitude of the phase difference. (See output waveform) The motor is driven. This concludes the general description of this embodiment. A more detailed explanation will be given below based on the circuit diagram shown in FIG. Figure 6 A and B have the relationship as shown in Figure 6 B, and points A, B, C, D, and E in Figure 6 A,
Point F, point G, and point H are points a and b in Figure 6 B, respectively.
It coincides with point, c point, d point, e point, f point, g point, and h point. Also, the same parts as in FIG. 2 are denoted by the same reference numerals. In the figure, 10 is a counter circuit that outputs the control output signal A. As mentioned above, the number of inputs is modulated (increase, decrease) by the command pulse.
clock pulse CPM is given,
A control output signal A is output based on this clock pulse CPM. 21 is a decimal counter and clock pulse
One clock pulse every 10 CPM counts
Output CPN. 22 is also a decimal counter,
1 for every 10 clock pulses CPN counted.
Outputs the starting clock pulse CPO. 23 is a T-type flip-flop, and the clock pulse
Repeats setting and resetting each time CPO is input. As a result, the T-type flip-flop 23 outputs a control output signal A having one period equal to the clock pulse CPM200. Based on the contents of this counter circuit 10, a 191 pulse signal, a 199 pulse signal, and a 0 to 7 pulse signal are created. These signals are input to the phase difference positive/negative detection circuit 11, and based on these signals and the resolver output signal B, it is detected whether the phase difference between the control output signal A and the resolver output signal B is positive or negative. AND gates 24 and 25 are gates for outputting 191 pulse signals, and AND gates 26,
27 is a gate for outputting a 199 pulse signal, and AND gate 28 is a gate for outputting a 0 to 7 pulse signal. In this embodiment, 191 pulse signals, 199 pulse signals,
Although the configuration is configured to detect whether the phase difference is positive or negative using 0 to 7 pulse signals, the signal for detecting the positive or negative phase difference is not limited to these signals, and various types can be selected. Fig. 7 shows control output signal A, 191 pulse signal, 199
The waveforms of pulse signals and 0 to 7 pulse signals are shown. Before explaining the phase difference positive/negative detection circuit 11, the resolver, which is a position detector, will be explained. 29 is a resolver. The resolver 29 has a rotating body 30 that rotates in conjunction with the rotation of the motor, and the rotating body 30 has two windings R ₁ -R ₃ and R ₂ -R ₄ . Further, S ₁ -S ₂ are stator output windings of the resolver 29. The two windings R ₁ -R ₃ and R ₂ -R ₄ of the rotating body 30 each receive a sine wave whose phase is shifted by 90 degrees (its period is the same as that of the reference signal). be done. A sine wave whose phase is shifted from the input sine wave by an amount corresponding to the rotation angle of the rotating body 30 is output to the stator output windings S ₁ -S ₂ . This sine wave is input to a filter amplifier 31. Furthermore, the output of the filter amplifier 31 is connected to the inverter 32.
is input into the resolver output signal B, which is waveform-shaped.
is output as The configuration of a circuit that supplies input sine waves whose phases are shifted by 90 degrees to the two windings R ₁ -R ₃ and R ₂ -R ₄ of the rotating body 30 is as follows. In FIG. 6B, 33 is a 50-decimal counter, which outputs one clock pulse CPP every time 50 reference clock pulses CP are counted. 34 is a T-type flip-flop which is repeatedly set and reset each time a clock pulse CPP is input. The set output of T-type flip-flop 34 is applied to the input of T-type flip-flop 35, while the reset output is applied to the input of T-type flip-flop 36. Both T-type flip-flops 35 and 36 are repeatedly set and reset at the falling edge of the input signal. Therefore, the T-type flip-flops 35 and 36 each output a rectangular wave whose period is the same as that of the reference signal and whose phases are shifted by 90 degrees from each other. This square wave is input to the filter amplifier 37,
converted to a sine wave. Further, the output of the filter amplifier 37 is input to transformers 38 and 39, and the outputs of the transformers 38 and 39 are supplied as input sine waves to the two windings of the resolver rotating body 30, respectively. Next, the configuration of the phase difference positive/negative detection circuit 11 will be explained. The phase difference positive/negative detection circuit 11 detects the positive/negative phase difference only when the phase difference between the control output signal A and the resolver output signal B is within the range of ±90°. The inverting amplifier 19 outputs a DC voltage proportional to the magnitude of the phase difference, as described above. This output is supplied to the input terminal of inverter 40. This inverter 40 is an inverter whose transistor is turned on when the input voltage is above a certain value (a voltage corresponding to a phase difference of 90° or above). The output of the inverter 40 is given to one input of an AND gate 41. The other input of the AND gate 41 is supplied with the resolver output signal B. The output of the AND gate 41 is input to the phase difference positive/negative detection circuit 11. Therefore, only when the output of the inverter 40 is "1" (when the phase difference between the two signals is within 90 degrees), the AND gate 41 inputs the resolver output signal B to the phase difference positive/negative detection circuit 11 and detects the phase difference positive/negative. The detection circuit 11 determines whether the phase difference is positive or negative. The AND gate 42 receives the 191 pulse signal as one input, and has the other input as the AND gate 4.
This is an AND gate that is given an output of 1. The AND gate 43 is an AND gate which receives the 199 pulse signal as one input and receives the output of the AND gate 41 as the other input. The explanation will be continued below with reference to FIG. [When resolver output signal B is (1) (positive phase difference)] It is assumed that the phase difference is within the range of ±90°. As shown in FIG. 7A, a one shot mono multivibrator 44 is set by the output signal of the AND gate 42. This set output is applied to one input of AND gate 45. and gate 4
The other three inputs of 5 are as follows. 1 Reset output of the one-shot mono multivibrator 46. 2 199 pulse signal. 3 AND gate 4 whose two inputs are the reference clock pulse CP and the inverted signal of the resolver output
7 output signal. The resolver output signal is "0" when the 199 pulse signal is output. Therefore, AND gate 45 outputs an output signal when the 199 pulse signal is output, and flip-flop 48 is set. This determines that the phase difference is positive. [When the resolver output signal B is (2) (negative phase difference)] As shown in FIG. 7B, the one shot mono multivibrator 46 is set by the output signal of the AND gate 43. This set output is applied to one input of AND gate 49. and gate 49
The other two inputs of are as follows. 1 Output signal of the AND gate 47. 2 0-7 pulse signal. Resolver output signal B when outputting 0 to 7 pulse signals
When becomes "0", the AND gate 49 outputs an output signal and resets the flip-flop 48. This determines that the phase difference is negative. In addition, one-shot mono multivibrator 44
is configured to maintain the set state until the 199 pulse signal is output, and the one shot mono multivibrator 46 is configured to maintain the set state for the output time of the 0 to 7 pulse signal. As is clear from the above configuration, the phase difference between the control output signal A and the resolver output signal B is within 90 degrees, and the fall time of the resolver output signal B is
The positive/negative phase difference is detected only between 191 pulses and 7 pulses. Furthermore, the phase difference varies smoothly due to the inertia of the motor and the smooth generation of command pulses, so a phase shift of more than 191 to 7 pulse signals does not occur. That is,
For example, there is no instantaneous jump from a 10 pulse signal to a 180 pulse signal. Therefore, in other states, the state of the flip-flop 48 does not change at all, and the previous determination result is maintained. Next, the configuration of the phase difference detection circuit 12 will be explained. A control output signal A is input to the AND gate 50, and an inverted signal of the control output signal A is input to the AND gate 51. Further, an inverted signal of the resolver output signal B is applied to the other input of the AND gates 50 and 51 via a differentiating circuit 52. This is to detect when the resolver output signal B falls. Therefore, when the resolver output signal B falls, if the control output signal A is "1", the AND gate 50 outputs an output signal, and if it is "0", the AND gate 51 outputs an output signal. The output signal of AND gate 50 is AND gate 5
3 and 54. The other input of the AND gates 53 and 54 is a flip-flop 48 for determination of the phase difference positive/negative detection circuit 11.
A set output and a reset output are provided respectively. On the other hand, the output signal of AND gate 51 is given to one input of AND gates 55 and 56. The other inputs of AND gates 55 and 56 are supplied with the reset output and set output of flip-flop 48, respectively. The output of AND gates 53 and 55 is OR gate 5
The output of OR gate 57 is applied to the set input of flip-flop 58. On the other hand, the outputs of AND gates 56 and 54 are applied to the input of OR gate 59, and the output of OR gate 59 is applied to one input of AND gate 60. The other input of the AND gate 60 is supplied with the inverted output of the inverter 40, which outputs "0" when the phase difference is 90 degrees or more. The output of AND gate 60 is applied to the reset input of flip-flop 58. As is clear from the above configuration, the phase difference 1 is determined to be positive, and the control output signal A becomes "1" when the resolver output signal B falls.
2 When the phase difference is determined to be negative and the signal A is "0" at the falling edge of the signal B, the OR gate 57 outputs an output signal and the flip-flop 5
8 is set. As a result, it is determined that the magnitude of the phase difference is in the range of (360×n)°-(360×n+180)°. (Refer to the output waveform of the set signal of the phase difference detection circuit 12 in FIG. 8 101) Also, 1. When the phase difference is determined to be positive and the signal A is "0" at the falling edge of the signal B, 2. The phase difference is When the signal A is determined to be negative and the signal A is "1" at the falling edge of the signal B, the OR gate 59 outputs an output signal, and the flip-flop 58 is reset via the AND gate 60. As a result, the magnitude of the phase difference is (360
×n+180)°-(360×n+360)°. (See the output waveform of the reset signal of the phase difference detection circuit 12 in FIG. 8 101.) The output of the OR gate 59 is
The reason why the signal is applied to the reset input of the flip-flop 58 via the (inhibition gate) is as follows. That is, when the phase difference is around 0°, the output of the phase difference positive/negative detection circuit 11 is not stable, and the OR gate 59 may output an output signal by mistake. This is to prevent such an output signal from being applied to the reset input of the flip-flop. The AND gate 60 prohibits output within a phase difference range of ±90°. The reset output and set output of the flip-flop 58 in the phase difference detection circuit 12 are respectively connected to a MOS field effect transistor (hereinafter referred to as MOSFET) which constitutes the analog switch 61 in the analog gate 18.
That's what it means. ) 62 and 63 are applied to the gate electrodes. These MOSFETs 62 and 63 are of a P channel enhancement type that becomes conductive when the gate input is "0". In other words, it is a negative logic; for example, the reset output from flip-flop 58 to MOSFET 62 is "0" and the set output to MOSFET 63 is "1".
When , MOSFET 62 becomes "1". On the other hand, the outputs of the first filter circuit 14 and the second filter circuit 15 are applied to the sources of the MOSFETs 62 and 63, respectively. Also MOSFET6
The drains of 2 and 63 are commonly connected to the input of an inverting amplifier 64, and the output of the inverting amplifier 64 becomes the output of the analog gate 18. The output of the analog gate 18 is applied via an inverting amplifier 19 to the source of a MOSFET 66 constituting an analog switch 65 in the analog gate 20. On the other hand, the output of the analog gate 18 is directly connected to the MOSFET constituting the analog switch 65.
It is given in 67 sources. The gate of the MOSFET 66 is supplied with the set output of the flip-flop 48 constituting the phase difference positive/negative detection circuit 11, and the gate of the MOSFET 67 is supplied with an inverted output of the set output. The drains of the MOSFETs 66 and 67 are commonly connected and connected to the input of an inverting amplifier 68, and the output of the inverting amplifier 68 is given to the motor drive circuit as the output of the analog gate 20. Next, the bias voltage output circuit 17, which is a feature of the present invention, will be explained. Inverting amplifier 19 in Figure 6B
Inverters 69, 70, whose inputs are the outputs of
Reference numerals 71 and 72 each indicate an inverter whose transistor is turned on when the input voltage exceeds a certain level. 69 is turned on when the input voltage V ₁ (the output voltage of the inverting amplifier 19 when the phase difference is 450°) is exceeded. 70 turns on when the input voltage is equal to or higher than the input voltage V ₂ (the output voltage of the inverting amplifier 19 when the phase difference is 270°). 71 turns on when the input voltage is equal to or higher than the input voltage V ₃ (the output voltage of the inverting amplifier 19 when the phase difference is 810°). 72 is turned on when the input voltage V ₄ (the output voltage of the inverting amplifier 19 when the phase difference is 630°) is exceeded. Transistor base resistance 69R,......,7
By adjusting the value of 2R, the threshold voltage of the inverter can be adjusted. The output of inverter 69 and the inverted output of inverter 70 are provided to the input of AND gate 73. Therefore, the AND gate 73 has a phase difference of 270°−450
The output becomes "1" in the range of . On the other hand, the output of inverter 71 and inverter 72
The inverted output of is given to the input of AND gate 74. Therefore, the output of the AND gate 74 becomes "1" within the phase difference range of 630°-810°. The output of the AND gate 73 is the AND gate 75,
76 is applied to one input. The other input of the AND gate 75 is supplied with the set output of the flip-flop 58 of the phase difference detection circuit 12, and the other input of the AND gate 76 is supplied with the reset output. The output of AND gate 75 is flip-flop 7
The output of AND gate 76 is applied to the reset input of flip-flop 77. The output of the AND gate 74 is the AND gate 78,
79 is applied to one input. The other input of the AND gates 78 and 79 has a phase difference detection circuit 1.
The set output and reset output of two flip-flops 58 are respectively provided. The output of AND gate 78 is flip-flop 8
The output of AND gate 79 is applied to the reset input of flip-flop 80. Furthermore, the flip-flop 5 of the phase difference detection circuit 12
The set output No. 8 is applied to the gate electrode of a MOSFET 82 constituting an analog switch 81. Bias voltage v ₁ is applied to the source of MOSFET82.
is supplied. The value of this bias voltage v ₁ is
The phase difference between control output signal A and resolver output signal B is
Equal to the first filter circuit output voltage at 180°. Further, the reset output of the flip-flop 77 is applied to the gate electrode of the MOSFET 83.
A bias voltage v ₂ is supplied to the source of the MOSFET 83. v ₂ = 2v ₁ . The reset output of flip-flop 80 is applied to the gate electrode of MOSFET 84. A bias voltage v ₂ is supplied to the source of the MOSFET 84. The drains of the MOSFETs 82, 83, and 84 are commonly connected to the output point of the analog switch 61. The bias voltage output circuit 17 is configured as described above. (Refer to the output waveform of the bias voltage output circuit 17 in FIG. 8 104) The operation of the position control circuit of this embodiment having the above configuration is summarized in Table 1 below. The operation of this embodiment is clear from Table 1.

[Table] FIG. 8 shows a waveform diagram of the overall operation. 101 is the output of the phase difference detection circuit 12, which is set when the magnitude of the phase difference is in the range of (360 × n) ° - (360 × n + 180) °, and (360 × n + 180) ° - (360 × n + 360). It is reset when the value is within the range of °. 102 is the output of the first filter circuit 14, which is the output of the exclusive logic circuit 13 when the phase difference is (360
xn)° - (360xn+180)°, the output is a DC voltage proportional to the increase in the magnitude of the phase difference. 103 is the output of the second filter circuit 15, which is the output of the exclusive logic circuit 13 which has been inverted by the inverter 16, and the magnitude of the phase difference is (360×n+180)°−
The output is a DC voltage proportional to the increase in the phase difference within the range of (360×n+360)°. 104 is the output of the bias voltage output circuit 17;
Inverting amplifier 19, phase difference detection circuit 1
This is the output after performing the operations summarized in Table 1 on page 30 based on the output of step 2. 105 is the output of the analog gate 18, which converts the outputs of the first filter circuit 14, second filter circuit 15, and bias voltage circuit 17 into a DC voltage that is correctly proportional to the magnitude of the phase difference based on the output of the phase difference detection circuit 12. This is the combined output. 106 is the output of the analog gate 20, which is the output of the analog gate 18 or the analog gate 18.
This is an output selected from one of the outputs through the inverting amplifier 19 based on the output of the phase difference positive/negative detection circuit. In the above example, the maximum bias voltage value is 5v ₁
However, it will be obvious that this value can be increased or decreased arbitrarily. Furthermore, in the above embodiment, the position of the tool, ie, the cutting tool, was controlled by the rotation of the motor, but the present invention can also be implemented in devices where the position of a table, saddle, etc. is controlled by the rotation of the motor. It is. The present invention can also be implemented in a position detector that uses something other than a resolver. As explained in detail above, according to the present invention, even when the phase difference between the control output signal A and the output signal B of the position detector exceeds the range of ±180°, an output voltage that is correctly proportional to the phase difference is output. , it is possible to provide a position control circuit in a numerical control device that can control a machine tool. In other words, even if you create a program to increase the feed speed when empty feeding a cutting tool, or in other words, if you create a program so that the phase difference exceeds the range of ±180°, it will still be correctly proportional to the phase difference. Accordingly, it is possible to provide a position control circuit that outputs a certain output voltage and can move a cutting tool at a predetermined speed. Furthermore, it can be realized with a relatively simple circuit configuration.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the numerical control system.
FIG. 2 is a block circuit diagram showing an embodiment of the present invention, FIG. 3 is a diagram for explaining the definition of positive and negative phase differences between the control output signal and the resolver output signal in the same embodiment, and FIG. The figure is a diagram explaining the principle of the phase difference detection circuit in the same embodiment, Figure 5 is a diagram showing the output voltage waveforms of the first filter circuit and the second filter circuit in the same embodiment, and Figures 6A and 6B are diagrams showing the output voltage waveforms of the first filter circuit and the second filter circuit in the same embodiment. 7 is a detailed circuit diagram showing the configuration of the same embodiment, FIGS. 7A and 7B are time charts for explaining the same embodiment, and FIG. 8 is a waveform diagram of the overall operation in the same embodiment. code, 3: position control circuit, 4: motor, 5: bite, 9: resolver, 11: phase difference positive/negative detection circuit, 12: phase difference detection circuit, 13: exclusive OR circuit, 14: first filter circuit, 15: Second filter circuit, 17: Bias voltage output circuit, 18:
Analog gate, 19: Inverting amplifier, 20: Analog gate, 29: Resolver,
A: Control output signal, B: Resolver output signal.

Claims (1)

[Claims] 1. In a numerical control device that controls the position of a table, saddle, tool, etc. by rotation of a motor, a control output signal whose phase is modulated by a command signal and an output of a position detector. Detects the phase difference with the signal,
Position control configured to control the rotational direction and rotational speed of the motor by applying a DC voltage having a predetermined polarity and magnitude to the motor based on the positive/negative of this phase difference and the magnitude of the phase difference. The circuit comprises: a phase difference positive/negative detection circuit for detecting whether the phase difference between the control output signal and the output signal of the position detector is positive or negative; The magnitude (absolute value) of the phase difference is (360×n)゜−(360
×n+180)° or (360×n+
180)° - (360×n+360)° (where n is 0 or a positive integer); an exclusive OR circuit as an input; a first filter circuit that converts the output signal of the exclusive OR circuit into a DC voltage proportional to the pulse width of the output signal and outputs it; and the exclusive OR circuit. a second filter circuit that converts the inverted output signal of the inverted output signal into a DC voltage proportional to the pulse width of the inverted output signal and outputs it; The magnitude (absolute value) of the phase difference of the output signal is within the range of (360 × m/2) ° - (360 × m / 2 + 180) ° to (360 × m / 2 + 180) ° - (360 × m / 2 + 360) )° [or when the phase difference changes within the range of (360×m/2+180)° – (360×m
/2 +360)° to (360×m/2)° – (360×m
/2 +180)°], the bias voltage output circuit increases (or decreases) the output bias voltage by a certain amount step by step (however, m is 0).
or a positive integer), based on the output of the phase difference detection circuit, the control output signal and the output signal of the position detector from the output of the first filter circuit or the second filter circuit and the output of the bias voltage output circuit. a DC voltage output circuit that synthesizes and outputs a DC voltage proportional to the phase difference of the DC voltage output circuit; and a circuit for supplying a proportional DC voltage of a predetermined polarity to the motor.