JPS61144921A - Reset pulse generating circuit - Google Patents

Abstract

PURPOSE:.To decrease the number of externally mounted components by applying large scale circuit integration to a logical section, forming a noise preventing circuit with a logical circuit and incorporating the circuit in the inside of the LIS. CONSTITUTION:When a signal is at an H level, a reset pulse generating circuit is in the scan mode, input signals of a-1-a-4 are propagated as they are in an incrementer 3, inputted to a holding circuit, where the signals are held by a CLK signal. An input signal (c) is given to a reset switch of a circuit 2 and a reset pulse generating circuit is transited to the load mode with the signal at an L level. The incrementer 3 is not operated and an output signal of the control circuit 2 is stored as it is in a holding circuit 4. The state is kept until the input to the control circuit is changed. When the signal (c) goes to H by the operation of an external switch 1, the count mode is attained, the incrementer 3 is operated and a data incremented by 1 is stored in the holding circuit 4 together with the output of the control circuit 2. The count-up is repeated sequentially in the count mode by the same procedure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a reset pulse generation circuit for a device, and in particular to prevention of noise in mechanical contact signals and noise prevention of a signal line from a signal generation source to a reset signal generation circuit. The present invention relates to a reset pulse generation circuit suitable for removing disturbance noise.

[Background of the invention]

The conventional reset signal generation circuit is disclosed in Japanese Patent Application Laid-Open No. 58-1755.
No. 21, q# Kaisho 58-175522, Japanese Patent Kokai Show 58-
As described in Japanese Patent No. 175323, etc., a reset signal is generated when the power supply voltage rises, and a reset failure due to ripples and noise of the power supply at this time is prevented. However, reset by reset switch 1
No consideration was given to disturbance noise caused by switch chatter, static electricity noise, etc. when No. g occurred.

[Purpose of the invention]

The purpose of the invention is to detect a mechanical contact signal, remove chattering generated from the mechanical contact signal, and quantitatively remove disturbance noise generated between the interface from the mechanical contact signal to the reset pulse generation circuit. It is also an object of the present invention to provide a reset pulse generation circuit necessary for resetting the device.

[Summary of the Invention] A conventional reset pulse generation circuit detects a mechanical contact signal and generates a reset pulse of a width necessary to initialize the device. In addition, noise removal using mechanical contact signals consisted of an integrating circuit using resistors and capacitors. In the present invention, the logic section is made into an LSiJ, and in order to reduce the number of external parts as much as possible, the noise prevention circuit is realized with a logic circuit, and the LS is incorporated internally, reducing the number of external parts. be.

[Embodiments of the invention]

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention.

In the figure, 1 is a system reset switch mounted on the operation surface of the device, 2 is a control circuit that controls input signals and the output of the holding circuit, 3 is an incrementer circuit connected to the output of the control circuit 20, and 4 is a 3 A plurality of holding circuits are connected to the outputs of the incrementer circuits. The input signal α of the second control circuit is a scan-in signal for increasing the diagnostic efficiency of the holding circuit.

When this signal is at level H, the reset pulse generation circuit is in scan mode and the input signals α-1 to α-4 are
The data is propagated through the incrementer No. 3 as is, input into the data of the holding circuit No. 4, and held by the CLK signal. During normal operation of the device, this signal is fixed at 1L level, and the circuit cannot enter scan mode, so the circuit is only intended to improve the diagnostic rate. b is a count pulse signal, and a constant pulse signal is always supplied.

Input signal C is connected to the reset switch of the device'''
In this state where the LL level is reached, the reset pulse generating circuit is transitioned to the load mode. Further, in this state, the incrementer 3 does not operate and the output signal of the control circuit 20 is stored as it is in the holding circuit 4. This state is maintained until the input of the 20 control circuit changes. When the C signal becomes H' by operating the external switch No. 1, the count mode is entered, and the incrementer No. 5 operates, and the data obtained by incrementing the output of the control circuit No. 20 by 1 is stored in the holding circuit No. 4. In the siccant mode, the count up is repeated in sequence using the same procedure.
return. FIG. 2 shows a time chart during operation of the logic circuit shown in FIG. When the C signal is at the 'L' level, the present reset pulse generation circuit transits to the load mode, and the output signals f and cL of the holding circuit are fixed at 1001'.

When the reset switch No. 1 is operated, the C signal becomes the ``H level'' and the υ count mode is entered, and the output signals of the holding circuit are 1010' and '1011'.

Count up as '1100'. If the reset switch signal has a pulse width that is not maintained until the output of the holding circuit counts up to 1100''?, the reset pulse generation circuit transitions to load mode and the output of the holding circuit changes to 1001' again. If the signal maintains the count value '1100' of the holding circuit,
At this point, the reset pulse f has the rising counter value '1'.
The issuance of the reset pulse f continues until 111'. At the same time, when the count value reaches '1100', the load condition of the control circuit 2 is suppressed and the count up is continued regardless of the state of the reset switch signal thereafter, and the count value 'o o
The count-up continues until o o', at which point the load inhibition is canceled and the load mode is entered again, and the p counter value changes to '1001'. According to this embodiment, it is possible to quantitatively remove the noise of the switch signal and the disturbance noise generated in the signal line from the switch signal generation source to the reset pulse generation circuit. , the mechanical contact signal noise generated from the reset switch and the disturbance noise can be quantitatively set to eliminate noise width by changing the period of the count pulse and assigning the counter value to the output Ig. .

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment. DESCRIPTION OF SYMBOLS 1... System reset switch, 2... Combinational logic circuit, 3... Increment circuit, 4... Holding circuit.

Claims (1)

[Claims] 1. A reset pulse generation circuit comprising an incrementer circuit and a plurality of holding circuits, characterized in that a control circuit is provided for controlling the state of the reset pulse generation circuit according to the state of an input signal.