JPS61144158A - Response detecting circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous response detection by providing a voltage dividing circuit between both ends and the earth of a resistance inserted serially to a calling signal sending line, and applying the whole wave rectification to the output, and comparing the result. CONSTITUTION:A relay 3 for sending a calling signal is operated by an exchange control circuit (not shown in the figure), and the contact is changed over, and then, a calling signal from a calling signal source 5 is sent through a resistance 4 to a subscriber telephone set 1. Between both ends of the resis tance 4 and the earth, a voltage dividing circuit 11 is installed, the pressure output is rectified at respective whole wave rectifier circuits 12-1 and 12-2, and sent to a comparing circuit 13. The output of a comparing circuit 13 is sent to a counting holding circuit 15 together with the clock signal corresponding to a half period of the calling signal obtained from a clock signal generating circuit 14. When a subscriber responds, the descending of the voltage of both ends of the resistance 4 goes to be larger, the output can be obtained at a comparing device 13 and therefore, the response can be detected without fail.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a response detection circuit in an automatic exchange.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional response detection circuit. In the figure, a resistor 4 detects the voltage by the current flowing through the subscriber line 2, and a low-pass filter (hereinafter referred to as LPF) that passes the DC component of the voltage generated across the resistor 4.
7. Full-wave rectifier circuit (hereinafter referred to as RE) that rectifies the output of LPF7.
8, a conversion circuit 9 including an optical coupling element and for coupling the output of the RECT 8 to a logic circuit, and a clip-flop (hereinafter referred to as FF) 1O for holding the output of the conversion circuit 9.

In addition, 3 is a contact point of a relay for sending out a calling signal, 2 is a subscriber telephone, 5 is a calling signal source, and 6 is a DC superimposed power supply for detecting a response.

Next, an outline of the operation of the conventional response detection circuit will be explained. First, the call signal sending relay 3 is operated by the exchange control circuit and its contacts are switched. As a result, the calling signal from the calling signal source 5 superimposed on the DC power source 6 is transmitted to the resistor 4,
It is sent out via relay contact 3 and subscriber line 2 to subscriber telephone l. The ringing signal current flowing through the subscriber telephone 1 causes an AC voltage drop across the υ resistor 4, but this voltage is attenuated by the LPF 7, so the output of the RECT 8 is sufficiently small. Therefore, no output appears in the conversion circuit 9 and F
F10 is not set.

On the other hand, when the subscriber answers, a DC closed circuit is formed in the subscriber's telephone L, so that the DC current is transmitted to the resistor 4 along with the ringing signal current.
flows to The DC voltage generated across the resistor 4 is rectified by the RECT 8 without being attenuated by the LPF 7, and an output signal for setting FF 10 appears at the output of the conversion circuit 9.

The exchange control circuit detects the set state of F F 10 and learns the subscriber's response.

[Problems to be solved]

As explained above, in the conventional response detection circuit, the AC voltage component and the DC voltage component generated across the resistor 4 are
Response detection is performed by discrimination using F7 and detection of the DC component. By the way, the frequency of the calling signal is a low frequency of around 20 Hz), and if the amount of attenuation of the AC component of the LPF 7 is not sufficient, the output of the AC component will be rectified by the RECT 8, which may cause erroneous response detection. -1 If the amount of AC component attenuation of the LPF 7 is increased to prevent false response detection, the time constant of the LPF 7 increases accordingly, resulting in a problem that the time from the subscriber response to obtaining the response detection output becomes longer. Ta.

[Means for solving problems]

The present invention solves the above problems, and includes a response detection circuit that detects the response of a subscriber's telephone when sending out a calling signal, in which both ends of each resistor inserted in series with the calling signal sending line are connected to the ground. In between, a voltage divider circuit, a clock signal generation circuit that generates a clock signal every half cycle of the calling signal, a circuit that full-wave rectifies the output of each of the voltage divider circuits, and a circuit that performs full-wave rectification of the output of each of the voltage divider circuits; It is comprised of a comparison circuit that compares outputs, and a circuit that counts and holds the output of the comparison circuit using the clock signal.

〔Example〕

Next, an example thereof will be explained with reference to FIG. 1 and an FGZ diagram.

FIG. 1 is a block diagram of a simple embodiment of a response detection circuit according to the present invention, and FIG. 2 is a diagram showing signal waveforms of various parts of the circuit before and after a subscriber response. The same parts as in FIG. 3 are given the same reference numerals.

In FIG. 1, reference numeral 11 is a voltage dividing circuit including a resistor and a capacitor, and a full-wave rectifier circuit 12-1, 12-2 and a comparator circuit are connected to the subsequent stage to divide the voltage between both ends of each resistor 4 and the earth. [3] and to attenuate the voltage to a voltage suitable for the clock signal generation circuit L4. Full wave rectifier circuit 12-1
, 12-2 is a resistor 4 divided by the voltage dividing circuit 11.
Full-wave rectification of the alternating current voltage between both ends of each terminal and the earth. The comparator circuit 13 generates an output only when the difference between the output voltages of the full-wave rectifier circuits L2-1 and 12-2 exceeds a predetermined value.

The clock signal generation circuit [4 generates a clock signal with a constant time width at the wavefront of every half cycle of the output of the full-wave rectifier circuit 12-2.

The counting and holding circuit 15 is provided to count and hold the output of the comparator circuit 13 using the clock signal from the clock signal generating circuit [4].

Next, each of the signals a and b in FIG. Also, each signal c, d of (0, (2)) in the same figure
is a rectified waveform obtained by the full-wave rectifier circuit 12-1.12-2. Also, the signal e in the same figure (g) is a comparison output waveform obtained by the comparison circuit [3]. Further, the signal f shown in (3) in the same figure is the clock signal output waveform of the clock signal generation circuit [4], and the signal g shown in (G) in the same figure shows the output waveform of the counting and holding circuit 15.

In this embodiment, in the state before the subscriber responds, the impedance of the subscriber telephone 1 is high, so the ringing signal current flowing through the subscriber line 2 is small, and the voltage difference between both ends of the resistor 4 and the ground is also small. Therefore, as shown in FIG. 2, the comparison circuit L3
The output signal e does not appear. On the other hand, when the subscriber answers, a DC closed circuit is formed in the subscriber's telephone 1, and the impedance decreases, so that the ringing signal current increases. For this reason, Figure 2 (
As shown in A) and (B), the voltage between the subscriber line side of the resistor 4 and the earth is sufficiently smaller than the voltage between the calling signal source side of the resistor 4 and the earth. As a result, as shown in FIG. 2(g), the output signal e of the comparator circuit L3 appears as a pulse as a differential output that is greater than a certain value of the voltages applied to the two inputs.

This output pulse appears near the wave crest of every half cycle of the calling signal, and is counted and held in the counting and holding circuit 15 using the clock pulse f from the clock signal generating circuit 14.

Since the counting circuit of the counting and holding circuit 15 is a counting circuit consisting of two stages of 7 limp flops, the response detection output g is generated within one cycle of the calling signal after the subscriber responds, as shown in Figure 2.
is obtained as the output of the counting and holding circuit 15. In addition, in order to prevent erroneous response detection that occurs due to transient phenomena in the subscriber line 2 when sending a ringing signal, the number of stages of the counting and holding circuit using the 7 limp flops in the counting and holding circuit 15 should be increased. can be dealt with effectively.

〔effect〕

As explained above, the present invention provides a response detection circuit that detects the response of a subscriber's telephone when sending out a calling signal, in which a voltage is applied between both ends of each resistor inserted in series in the calling signal sending line and the earth. A division circuit, a clock signal generation circuit that generates a clock signal every half cycle of a calling signal, a circuit that performs full-wave rectification of each output of the voltage division circuit, and a comparison that compares each output of the full-wave rectification circuit. Since the circuit and the circuit that count and hold the output of the comparison circuit using the clock signal are provided, there is an advantage that a response detection output can be obtained in a short time and that erroneous response detection can be prevented. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a response detection circuit according to the present invention, FIG. 2 is a diagram showing signal waveforms of each part of the circuit before and after a subscriber response, and FIG. 3 is a diagram of a conventional response detection circuit. It is a circuit diagram of a circuit. 1... Subscriber telephone 2... Subscriber line 3...
Calling signal sending relay contact 4... Voltage detection layer resistance 5... Calling signal source 6...
Superimposition DC power supply 7...Low pass filter (LPF) 8...Full wave rectifier circuit (RECT) 9...Conversion circuit lO...7 lip 70 amplifier 11...Voltage divider circuit 12- 1.12-2...Full wave rectifier circuit 13...Comparison circuit [4...Rink signal generation circuit 15...Counting, holding circuit

Claims (1)

[Claims] In a response detection circuit that detects the response of a subscriber's telephone when a ringing signal is sent out, a voltage dividing circuit is connected between each end of each resistor inserted in series in the ringing signal sending line and the earth, and a voltage dividing circuit is connected to the earth. a clock signal generation circuit that generates a clock signal for each output, a circuit that performs full-wave rectification of each output of the voltage divider circuit, a comparison circuit that compares each output of the full-wave rectification circuit, and a circuit that performs full-wave rectification of each output of the voltage division circuit; A response detection circuit comprising: a circuit that holds a count using the clock signal.