JPS61141179A - Turn-off thyristor - Google Patents

Turn-off thyristor

Info

Publication number
JPS61141179A
JPS61141179A JP26415384A JP26415384A JPS61141179A JP S61141179 A JPS61141179 A JP S61141179A JP 26415384 A JP26415384 A JP 26415384A JP 26415384 A JP26415384 A JP 26415384A JP S61141179 A JPS61141179 A JP S61141179A
Authority
JP
Japan
Prior art keywords
region
layer
type
thyristor
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26415384A
Other languages
Japanese (ja)
Other versions
JPH0580832B2 (en
Inventor
Mitsuteru Kimura
光照 木村
Fumihiko Sugawara
菅原 文彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP26415384A priority Critical patent/JPS61141179A/en
Publication of JPS61141179A publication Critical patent/JPS61141179A/en
Publication of JPH0580832B2 publication Critical patent/JPH0580832B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To contrive a reduction in current density and an augmentation in the maximum controllable current by a method wherein the respective passages for minority carriers and majority carriers, which are injected in the base region on one side, are separate-limited and high-impurity density regions, which have an inverse conductive type to the conductive type of the base region and are brought into a low-resistance state, and a gate are provided on the passage for the minority carriers. CONSTITUTION:When a positive voltage and a negative voltage and respectively impressed on an anode A1 and a cathode K, a positive pulse voltage is impressed on an N-type base layer Nb and a gate G is brought into a conducted state, electrons, which are injected in the layer Nb from an N-type emitter layer Ne, flow in a region B, the layer Nb and the N-type emitter layer Ne and bond with positive holes, while the majority of positive holes, which are injected in the layer Nb from the layer Ne, flow in low-resistance regions C as the potential of the region B is high and gap regions D are narrow, and further flow in a P type base layer Pb. Then, when a negative voltage is impressed on the gate G, the P-N junctions of the layer Nb and the P-type regions C are biased in the reverse direction, the positive holes which flowed in the regions C, are extracted through the gate G and the passage of the positive holes through the gap regions D is stopped by the gap regions D as the gap regions D respectively become the area of a depletion layer making a P-N junction. As a result, this turn-OFF thyristor is turned into an OFF-state layer.

Description

【発明の詳細な説明】 本発明は、サイリスタのゲートに電圧を印加し、サイリ
スタの導通状態から(逆)阻止状態に移行させる、いわ
ゆるターン・オフ・サイリスタにおいて、一つのベース
の領域を通過する多数キャリアと少数キャリアのうちへ
少数キャリアの流れを阻止することにより、サイリスタ
をターン・オフさせるため、多数キャリアと少数キャリ
アの通路を分離し、少数キャリアの通路をしゃ断するよ
うにしたターン・オフ・サイリスタに関するもので、大
電源のスイッチングに適するようにしたものである。p
apna!サイリスタをflfifl形トランジスタと
npn形トランジスタの組合せと考え、pIIp形トラ
ンジスタの゛、U流増幅率をdpnp 、npn形トラ
ンジスタの電流増幅妻をfXnpnとしたとき、従来の
ゲート・ターン・オフ・サイリスタ(G T O)では
一般にターン・オフ 利得を増加させるため・dpnp
とσnpnのうち大きい方のトランジスタのベースにゲ
ートGを設けている。しかし、このゲートGを設けたベ
ース層は、低抵仇率にできず、かつ、一般にその厚みを
小さくさせる必要があり、ベース抵抗が大きくなる。大
電流を制御しようとするGTOでは、ベース層厚みを薄
くしたまま、カソードおよびベース領域の面積を大きく
させるので、ベース抵抗が一〇増加し、このため、ター
ン・オフ時間は増加し、最大可制″a電流は、大きくで
きないという問題がある。また、ベース層の厚みを大き
くすれば、ターン、オフ利得が小さくなると共に、サイ
リスタ内での電力損失が増大するという問題があった。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called turn-off thyristor in which a voltage is applied to the gate of the thyristor and causes the thyristor to transition from a conducting state to a (reverse) blocking state, passing through the region of one base. In order to turn off the thyristor by blocking the flow of minority carriers into majority carriers and minority carriers, a turn-off device separates the paths of majority and minority carriers and cuts off the path of minority carriers. -Related to thyristors, which are suitable for switching large power supplies. p
apna! Considering a thyristor as a combination of a flfifl type transistor and an npn type transistor, and assuming that the current amplification factor of the pIIp type transistor is dpnp, and the current amplification wife of the npn type transistor is fXnpn, the conventional gate turn-off thyristor ( In order to increase turn-off gain in GTO), dpnp is generally used.
A gate G is provided at the base of the larger transistor of and σnpn. However, the base layer provided with this gate G cannot be made to have a low resistivity, and generally needs to be made small in thickness, resulting in a large base resistance. In a GTO that attempts to control large currents, the areas of the cathode and base regions are increased while keeping the base layer thickness thin, which increases the base resistance by 100%, which increases the turn-off time and increases the maximum possible There is a problem that the limiting a current cannot be increased.Also, if the thickness of the base layer is increased, there is a problem that the turn and off gain becomes smaller and the power loss within the thyristor increases.

本発明のターン・オフ・サイリスタは、従来のCTOの
上述の欠点をなくすように#l成したもので、要点を間
車に述べると次のようになる。一方のペース領域(領域
A)に注入された少数キャリアと多数キャリアの通路を
分離制限しておき、このうち、少数キャリアの通路に、
このペース領域(領域A)とは逆の伝道形で高不純物密
度のため低抵抗化している領域Cを少数キャリアの通路
をふさぐように形成し、この領域Cにゲートを設けてお
く。サイリスタの導通状態では、領域Aの少数キャリア
をほとんど領域Cを通過させ、サイリスタを阻止状態に
するには、領域Cを領域Aに対して、逆方向バイアスに
させるなどして、領域Cの電位を変化させて、領域Cを
通過するベース領域Aの少数キャリアを阻止する(ゲー
トGから抽出する)というもので、ゲートGをもつ領域
Cを高い不純物密度にして、低抵抗化できるので、容易
に領域Cの電位変化が達成でき、従来のGTOにおける
ゲートGを存するベースが大きなベース抵抗を持つとい
う問題が解決できる。更に、本発明のターン・オフ・サ
イリスタでは、普通、サイリスタを構成する二つのトラ
ンジスタのうち、電流利得の大きい方のトランジスタの
ベースには、ゲートを設けないか、または設けても、タ
ーン・オフ用のゲートとしないため、このトランジスタ
のベース領域の面積を大きくする必要はなく、相対的に
エミッタ領域の面積を大きくできるので、電流密度を減
少できる。また、ペース領域Aの多数キャリアと少数キ
ャリアの通路の分離を図るので、ベース領域Aの電流密
度も小さくでき、サイリスタの大電流時の局所的な加熱
を防ぐことができるので、大電力用に適する。
The turn-off thyristor of the present invention is designed to eliminate the above-mentioned drawbacks of the conventional CTO, and the main points can be summarized as follows. The paths of minority carriers and majority carriers injected into one pace region (area A) are separated and restricted, and among these, the path of minority carriers is
A region C, which has a conductive type opposite to this pace region (region A) and has a low resistance due to a high impurity density, is formed so as to block the path of minority carriers, and a gate is provided in this region C. When the thyristor is in a conductive state, most of the minority carriers in region A pass through region C. To put the thyristor in a blocked state, the potential of region C is changed by biasing region C in the reverse direction with respect to region A. The method is to block the minority carriers in the base region A passing through the region C (extract them from the gate G) by changing the The potential change in the region C can be achieved in a manner similar to that of the conventional GTO, and the problem that the base in which the gate G is located has a large base resistance can be solved. Further, in the turn-off thyristor of the present invention, the base of the transistor with the larger current gain among the two transistors constituting the thyristor is usually not provided with a gate, or even if a gate is provided, the turn-off thyristor cannot be turned off. Since the transistor is not used as an additional gate, there is no need to increase the area of the base region of this transistor, and the area of the emitter region can be relatively increased, so that the current density can be reduced. Furthermore, since the majority carrier and minority carrier paths in the pace region A are separated, the current density in the base region A can be reduced, and local heating of the thyristor at high currents can be prevented, making it suitable for high power applications. Suitable.

以ド、本発明のターン・オフ・サイリスクを実施例に基
づき、図面を参照しながら詳述する。第1図は、本発明
のpnpn構造を有するターン・オフ・サイリスタをシ
リコン(sl)のラテラル構造で実施した一実施例のア
ノードAiカソードにおよびゲートCを含む面の断面構
a図で、pHpH構ゐとは同図のp、 % pa n@
 a aに対応する。尚、I)e+ n&などの添字、
電とトは、それぞれエミッタ、ベースに対応させている
。fle n&Ph n、 a 造のサイリスタはpn
pn上形ンジスタ(lee % %で構成される)とn
p口形トランジスタ(”e Oh ”hで#l成される
)とに分割して考えることができ、第1図の実施例では
、IIpn形トランジスタの電流増幅率IXnpnが、
pnpn上形ンジスタの偏流増幅率C1pnpより大き
いとしている。抵坑率0.015 fl−cm程度の高
不純物密度のn形のシリコン基板(0“−3i基板)皿
を領域Bとし、この上のn形、抵抗率約10Ωrcm、
厚み約1シ員のエピタキシャル成長層具をn形ペース層
nhとする、このn形ベース層n&がベース領域Aに対
応している。このn形のエピタキシャル成長層具に、例
えば約すgI深さのp形エミッタ層pe+p形ベース層
p、およびカソードにを設けた深さ約9涜のn形エミッ
タ居neを第1図の如く形成し、更に、n形の低抵抗領
域Bから約Y蝿離し、p形の高不純物密度をもつ低抵抗
の領域Cを同図の如く形成してる。このような構成のタ
ーン・オフ・サイリスタの動作機構について説明すると
、次のようになる。直流電源から、負荷を通して、アノ
ードA、に正。
Hereinafter, the turn-off risk of the present invention will be described in detail based on embodiments and with reference to the drawings. FIG. 1 is a cross-sectional diagram of a plane including an anode Ai cathode and a gate C of an example in which a turn-off thyristor having a pnpn structure according to the present invention is implemented with a lateral structure of silicon (SL), and shows the pH The point is p in the same figure, %pan@
a Corresponds to a. Furthermore, I) subscripts such as e+n&,
Electric and G correspond to the emitter and base, respectively. The thyristor made of fle n & Ph n, a is pn.
pn upper type resistor (composed of lee%%) and n
The current amplification factor IXnpn of the IIpn-type transistor is, in the embodiment shown in FIG.
It is assumed that the drift amplification factor C1pnp of the pnpn upper type transistor is larger than that of the pnpn transistor. An n-type silicon substrate (0"-3i substrate) plate with a high impurity density with a resistivity of about 0.015 fl-cm is defined as region B, and an n-type silicon substrate with a resistivity of about 10 Ω rcm on top of this plate has a resistivity of about 10 Ω rcm,
The n-type base layer n& corresponds to the base region A, and the n-type space layer nh is an epitaxially grown layer having a thickness of about 1 cm. In this n-type epitaxial growth layer, for example, a p-type emitter layer pe + a p-type base layer p with a depth of about gI, and an n-type emitter layer ne with a depth of about 9cm provided at the cathode are formed as shown in Fig. 1. Furthermore, as shown in the figure, a p-type low-resistance region C having a high impurity density is formed about Y distance from the n-type low-resistance region B. The operating mechanism of the turn-off thyristor having such a configuration will be explained as follows. From the DC power source, through the load, to anode A, positive.

カソードKに負になるように電圧を印加しておきゲート
Gにn形ベースIdnbに対して正のパルス1C圧を印
加して、サイリスタを導通状態にした場合、n形エミッ
タ府n、からn形ベース府n、に注入された領域Aにお
ける多数キャリ号つある電子は、低抵抗である領域Bに
流入し、p形エミッタ層+1cの底部にある領域Bの部
分領域からn形ベース層na)こ流出し、ついにはp形
エミッタl1Iipeに流入して、このエミッタ居pe
の正孔と再結合する。一方、p形エミッタnpcからn
形ペースJFjn、に注入された少数キャリ援ン正孔の
大部分は、領域Bが、正孔に対してポテンシャルが高い
ため流入できず、また、すき開領域りは狭いため抵抗が
高く、低抵抗の領域Cに流入することになる。更に、領
域Cをn形ベース層nb (領域A)に対して、順方向
バイアスになるまで充電し、定常状態では、正孔は領域
Cを通過し、p形ベース層p−流入している。このサイ
リスタを(逆)阻止状態に移行させるには、ゲートGに
、n形ペース11In6に対して負の電圧を印加すれば
よい。このとき、n形ベース層n、とp影領域Cとの間
とpn!l!合は、逆方向バイアスされるので、循環C
に流入した正孔は、ゲートGを通して抽出され、再びn
形ベース層116にはもどることができない。また、領
域Cと領域Bとのすき1%[1域0の幅は、狭い(約f
気)上に、逆バイアスされたベース層fi−と領域Cの
pn#合の空乏層領域になるので、すき開領域りも正孔
の通過がしゃ断され、p形ベースII!jp、への正孔
の補給が断たれるために、サイリスタは阻止状@(オフ
状層)に移行することになる。本発明のターン・オフ・
サイリスタは、従来のラテラル形サイリスタと同様の工
程で作製できる。例えば、p形層p、lplおよび領域
Cは、ホウ素の熱拡散により形成でき、n形エミッタ層
n、は、リンの熱拡散により形成できる。絶縁体のSi
0.!! 4 + 4’+ 4”は、51の熱酸化によ
り0.57m程度形成すればよく、アノードA1用電極
11ゲートG用電極2およびカソードKffI電4i1
3は、オーム性電極で、アルミニウム(AI)の真空蒸
着膜を約か厚にし、フォトリソグラフィーによりパター
ン形成できる。
When a negative voltage is applied to the cathode K and a positive pulse 1C voltage is applied to the gate G with respect to the n-type base Idnb to make the thyristor conductive, the n-type emitters from n to n The electrons with the majority carrier number in region A, which are injected into the type base layer n, flow into the region B, which has a low resistance, and flow from the partial region of region B at the bottom of the p-type emitter layer +1c to the n-type base layer na. ) flows out, and finally flows into the p-type emitter l1Iipe, and this emitter
recombines with the hole. On the other hand, p-type emitter npc to n
Most of the minority-carried holes injected into the shaped pace JFjn cannot flow into region B because it has a high potential for holes, and the gap region is narrow and has high resistance and low It flows into the region C of resistance. Furthermore, region C is charged until it becomes forward biased with respect to the n-type base layer nb (region A), and in a steady state, holes pass through region C and flow into the p-type base layer p-. . To shift this thyristor into the (reverse) blocking state, a negative voltage with respect to the n-type pace 11In6 can be applied to the gate G. At this time, between the n-type base layer n and the p shadow region C, pn! l! is backward biased, so the circulation C
The holes flowing into are extracted through the gate G and are returned to n
It is not possible to return to the shaped base layer 116. Also, the gap between area C and area B is 1% [the width of area 0 is narrow (approximately f
Since the reverse biased base layer fi- and the pn# of the region C become depletion layer regions, the passage of holes is also blocked through the gap region, and the p-type base II! Since the supply of holes to jp is cut off, the thyristor shifts to a blocking state (off state). Turn-off of the present invention
The thyristor can be manufactured using the same process as a conventional lateral thyristor. For example, p-type layers p, lpl and region C can be formed by thermal diffusion of boron, and n-type emitter layer n can be formed by thermal diffusion of phosphorus. Insulator Si
0. ! ! 4 + 4' + 4'' may be formed by thermal oxidation of 51 to a length of about 0.57 m, and the electrode 11 for the anode A1, the electrode 2 for the gate G and the cathode KffI electrode 4i1
3 is an ohmic electrode, which can be patterned by photolithography using a vacuum-deposited film of aluminum (AI) with a thickness of about 100 ml.

第2図は、本発明のターン・オフ・サイリスタをStの
縦形naにして実施した一実施例の断面構造図であり、
第1図に示した実施例と同様の作用をする部分には、同
一の参照記号または、番号を付しである。第2図の実施
例では、第1図に示した実施例と同様、p@ n6 p
a ”4構造のサイリスタであり、npn形トランジス
タ部のp形ベース層9kにもゲートclを設けた場合の
例を示しである。もちろん、本発明の主旨は、ゲートc
lの有無には無関係である。第2図の縦形構造の実施例
に基づき、図面を参照しながらその作製方法の一例を詳
述すると次のようである。先ず、n形St (約10α
cm)の基板10’ (厚み約150.&L%)の表裏
両面にホウ素の熱拡散を行い、約19−の深さまで、p
形層であるp形エミッタNp、および領域Cとなるべき
p形高不純物密度層を形成する。この際、フォトリソグ
ラフィーにより、Si基板dの表面の領域Cの中央に約
1■■角のホウ素拡散のしていない領域を形成しておく
。このp形Jg@をしていない領域にリンをwh敬して
領域Bとなるべき潟不純物密度のn形層を、領域Cとこ
の領域Bとのすき開領域りの幅が約→担程度になるよう
に、深さIQ、gx程度拭敞する、次に、このすき間脩
域0を高抵抗化させるため、金(An)などを、すき開
領域に拡散する。もちろん、このすき開領域りをイオン
注入などで絶縁体化させたり、すき開領域をふさぐよう
に絶縁膜を形成して高抵抗化してもよい、1g!に、f
i影、抵抗′a10Ω・C謙程度、厚み1o/L慨程度
のエピタキシャル層11′を成長させ、その表面から領
域Cへの導通を図るためp形の深い不純物拡散(ホウ素
の拡散)を行い、p影領域ルを形成する。次に、ll1
1図のmwJと同様に、p形ベース層p6、n形エミッ
タ層n、を拡散形成し、絶縁および表面保護用の5IO
1膜4.4’、4’を熱酸化により形成し、更に、AI
電極1.2,2.3をパターン形成する。第2図に示し
た縦形のターン・オフ・サイリスタの動作原理は、第1
図に示したラテラル形のものと同様である。
FIG. 2 is a cross-sectional structural diagram of an embodiment in which the turn-off thyristor of the present invention is made into a vertical na of St.
Components that function similarly to those of the embodiment shown in FIG. 1 are given the same reference symbols or numbers. In the embodiment shown in FIG. 2, p@n6 p
This is an example of a thyristor having a 4 structure, in which a gate CL is also provided in the p-type base layer 9k of the npn-type transistor section.Of course, the gist of the present invention is that the gate c
The presence or absence of l is irrelevant. Based on the embodiment of the vertical structure shown in FIG. 2, an example of the manufacturing method will be described in detail with reference to the drawings as follows. First, n-type St (approximately 10α
Thermal diffusion of boron is performed on both the front and back surfaces of the substrate 10' (thickness: approximately 150.cm), and p
A p-type emitter Np, which is a type layer, and a p-type high impurity density layer, which is to become a region C, are formed. At this time, by photolithography, a region of about 1 square inch where boron is not diffused is formed in the center of region C on the surface of the Si substrate d. Add phosphorus to this p-type region without Jg@ to form an n-type layer with a lagoon impurity density that should become region B. The width of the gap between region C and this region B is approximately → Next, in order to make this gap region 0 high in resistance, gold (An) or the like is diffused into the gap region. Of course, this gap area may be made into an insulator by ion implantation, or an insulating film may be formed to cover the gap area to increase the resistance. ni, f
An epitaxial layer 11' with a resistance of about 10Ω/C and a thickness of about 10/L is grown, and deep p-type impurity diffusion (boron diffusion) is performed to establish conduction from its surface to region C. , p forming a shadow region. Next, ll1
Similar to mwJ in Figure 1, a p-type base layer p6 and an n-type emitter layer n are formed by diffusion, and 5IO for insulation and surface protection is formed.
1 film 4.4', 4' is formed by thermal oxidation, and then AI
Pattern the electrodes 1.2, 2.3. The operating principle of the vertical turn-off thyristor shown in Figure 2 is as follows:
It is similar to the lateral type shown in the figure.

本発明のターン・オフ・サイリスタのターン・オフ時の
ゲートGの[動は、外部に取りつけた小電力用のトラン
ジスタやサイリスタにより行うことができる。
The operation of the gate G during turn-off of the turn-off thyristor of the present invention can be performed by an externally attached low-power transistor or thyristor.

以上の説明から明らかなように、本発明によるターン・
オフ・サイリスタは、ベース領域を走行する多数キャリ
アと少数キャリアを分層するので、電流密度を小さくで
きること、このサイリスタを構成する二つのトランジス
タのうち、電流増幅率の大きい方のトランジスタのベー
ス層の厚みを小さくできると共に、そのトランジスタの
エミッタだの面積も相対的に大きくできることなどから
、大電力用に適する。また、ベース領域Aの少数キャリ
アの通過を制御する府である領域Cは、高い不純物密度
が可能なため、低抵抗にもでき容易にベース領域Aの少
数キャリアを引き出すことができるので、最大可制御電
流が大きくなり、かつ、高速動作となり得る。
As is clear from the above explanation, the turn and
An off-thyristor separates the majority carriers and minority carriers traveling in the base region, so the current density can be reduced. It is suitable for high power applications because the thickness can be reduced and the area of the emitter of the transistor can also be relatively large. In addition, since region C, which is a region that controls the passage of minority carriers in base region A, can have a high impurity density, it can also be made low in resistance and can easily draw out minority carriers in base region A. The control current becomes large and high-speed operation is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明によるターン・オフ・サイリスタをラ
テラル形に実施した一実施例のアノードA。 、ゲートGおよびカソードKを含む面における断面rl
a図、第2図は、本発明の他の実施例で、縦形に実施し
た場合の第1図と同様の断面n造図を示す。 10.10′・・・・n形基板、 旦、旦・・・・■形
エピタキシャル層、 [・・・・p形拡散醤域、1,2
12.3・・・・AI@極、 4.4’、4・・・・s
to、膜、A・・・・n形ベース領域、 B・・・・n
形高不純物密度領域、 C・・・・p@高不純物領域、
 O・・・・すき開領域、p、・・・・p形エミッタ島
、 n、・・・・n形ベース層、pHl・・・・p形ベ
ース層、fil・・・n形エミッタ唐 特許出顕へ 木村光照
FIG. 1 shows an anode A of an embodiment of a turn-off thyristor according to the invention in a lateral configuration. , cross section rl in a plane including gate G and cathode K
Figures a and 2 show another embodiment of the present invention, which is a cross-sectional diagram similar to that of Figure 1 when it is implemented vertically. 10.10'...n-type substrate, dan, dan...■-type epitaxial layer, [...p-type diffusion region, 1,2
12.3...AI@pole, 4.4', 4...s
to, film, A...n-type base region, B...n
type high impurity density region, C...p@high impurity region,
O... Gap region, p,... P-type emitter island, n,... N-type base layer, pHl... P-type base layer, fil... N-type emitter Tang patent To the emergence of Mitsuteru Kimura

Claims (1)

【特許請求の範囲】[Claims]  pnpn構造を有し、一方のベース領域Aにおける少
数キャリアp_a(またはn_a)の流れを阻止するこ
とにより導通状態から阻止状態に移行させるターン・オ
フ・サイリスタにおいて、ベース領域Aに、該ベース領
域Aと同一伝導形の領域Bとベース領域Aとは逆の伝導
形の領域Cとを設け、ベース領域Aのキャリアは、領域
Bと領域C、および領域Bと領域Cとのすき間領域D以
外は通過できないような構造にし、サイリスタの導通状
態では、ベース領域Aの少数キャリアp_a(またはn
_a)の少なくとも90%以上が領域Cを通過し、多数
キャリアn_a(またはp_a)の少なくとも90%以
上が、領域Bを通過するように、領域Bと領域Cとを高
不純物密度にさせると共に近接させて形成し、すきま領
域Dは、サイリスタの導通状態から阻止状態への移行の
際に、少数キャリアp_a(またはn_aが、通過でき
ないか、または、通過してもサイリスタの導通状態が維
持できないように狭くするか、または、高抵抗化して形
成し、サイリスタを、導通状態から阻止状態に移行させ
るのに、領域Cの電位を変化させて、領域Cを通過する
領域Aの少数キャリアp_a(またはn_a)の流れを
しゃ断することにより行うようにしたことを特徴とする
ターン・オフ・サイリスタ。
In a turn-off thyristor that has a pnpn structure and transitions from a conductive state to a blocking state by blocking the flow of minority carriers p_a (or n_a) in one base region A, the base region A is A region B of the same conductivity type as the base region A and a region C of the opposite conductivity type to the base region A are provided, and carriers in the base region A are distributed in regions other than regions B and C and a gap region D between the regions B and C. When the thyristor is in a conductive state, minority carriers p_a (or n
Region B and region C are made to have a high impurity density and are placed in close proximity so that at least 90% or more of __a) passes through region C and at least 90% or more of majority carrier n_a (or p_a) passes through region B. The gap region D is formed so that the minority carrier p_a (or n_a) cannot pass through the thyristor during transition from the conductive state to the blocked state, or the conductive state of the thyristor cannot be maintained even if the minority carrier p_a (or n_a) passes through. To move the thyristor from a conducting state to a blocking state, the minority carriers p_a (or A turn-off thyristor characterized in that the turn-off is performed by cutting off the flow of n_a).
JP26415384A 1984-12-13 1984-12-13 Turn-off thyristor Granted JPS61141179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26415384A JPS61141179A (en) 1984-12-13 1984-12-13 Turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26415384A JPS61141179A (en) 1984-12-13 1984-12-13 Turn-off thyristor

Publications (2)

Publication Number Publication Date
JPS61141179A true JPS61141179A (en) 1986-06-28
JPH0580832B2 JPH0580832B2 (en) 1993-11-10

Family

ID=17399198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26415384A Granted JPS61141179A (en) 1984-12-13 1984-12-13 Turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS61141179A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5025792A (en) * 1973-07-16 1975-03-18
JPS5783057A (en) * 1981-09-05 1982-05-24 Semiconductor Res Found Thyristor
JPS5799773A (en) * 1980-12-13 1982-06-21 Fuji Electric Co Ltd Composite thyristor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5025792A (en) * 1973-07-16 1975-03-18
JPS5799773A (en) * 1980-12-13 1982-06-21 Fuji Electric Co Ltd Composite thyristor
JPS5783057A (en) * 1981-09-05 1982-05-24 Semiconductor Res Found Thyristor

Also Published As

Publication number Publication date
JPH0580832B2 (en) 1993-11-10

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