JPS61140242A - Ciphering system - Google Patents

Abstract

PURPOSE:To attain ciphering with high secrecy by ciphering an assigned signal from an output channel assignment control circuit and switching plural address conversion means by a random number generator at random synchronously with the ciphering so as to make the order of trunks assigned to channels of a transmission line at random. CONSTITUTION:An assignment signal from an output channel assignment control circuit 5 is ciphered and transmitted by a ciphering device 30 using, e.g., a DES (data ciphering standards), the signal is decoded by a decoder 34 at the reception side, the original assignment signal is obtained and given to an assignment signal decoding section 10. N kinds of converting means comprising N-set of ROMs 1-1-1-N are provided to the transmission side so that a write address from an address line 20 is converted such as 1 into 2 by the ROM1-1, 1 into 3 by the ROM1-2<1 into 1+N by the ROM1-N. Further, N kinds of converting means comprising N-set of ROMs 2-1-2-N are provided so that the read address from an address line 21 is converted such as 1 into 2 by the ROM 2-1, 1 into 3 by the ROM2-2...1 into 1+N by the ROM2-N.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a TDMA system for improving the utilization efficiency of transmission lines.
DS used for (multiple access communication) etc. (Digita
1Speech II Interpolation) device encryption method.

Currently, DSI devices are not used much except for some international lines, but recently, development is progressing to introduce them into the field of medium- and long-distance domestic communication, and the provision of an encryption method is desired. There is.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram of a conventional DSI device, in which (A) shows the transmitting side, (B) shows the receiving side, and FIG. FIG. 2 is a diagram showing writing to, reading from, and transmission signals to the buffer memories 2 and 7 in the case shown in the figure.

In the figure, 1.8 is a delay circuit, 2 and 7 are buffer memories, 3 is a multiplexing unit, 4 is an audio detection unit, 5 is an output channel assignment control circuit, 6 is a noise insertion unit, 9 is a separation unit, and IO is an allocation unit. In the signal decoding section, 20 to 23 indicate address lines.

In FIG. 2(A), for example, digitally multiplexed audio signals of 48 input channels (CHs on the input side are called trunks) pass through a delay circuit 1, and then are sent to an address line of an output channel assignment control circuit 5. Figure 3 (A) from 20
The audio signals are stored in the buffer memory 2 in trunk order according to the write addresses in the numerical order shown in FIG.
write to.

On the other hand, the audio detection unit 4 determines whether or not there is an audio signal in the input trunk (for example, trunks 1, 3, 4, 6, 8, 9, 12° 13 in FIG. 3(B) are audio signals). (There is no audio signal in the shaded trunks 2°5.7, 10.11) This determination result is notified to the output channel assignment control circuit 5.

In response to this, the output channel allocation control circuit 5 sequentially reads only the audio signals of the trunks with audio signals at the address shown in FIG. Allocate to CH (frame time slot) in CH order. That is, as shown in FIG. 3(D), an assignment signal indicating the trunk number corresponding to the CH number and the presence/absence of CH assignment is sent to CH2 on the transmission path.
After that, allocate the trunk audio signal, Pufffa Memo U
A multiplexer 3 multiplexes the audio signal output from the output channel allocation control circuit 2 and the allocation signal output from the output channel allocation control circuit 5, and transmits the multiplexed signal as a transmission signal shown in FIG. 3(D).

On the receiving side, this is received, and the separation unit 9 separates the audio signal and the allocation signal.The allocation signal is sent to the allocation signal decoding unit IO, and the audio signal is sent to the buffer memory 7 via the delay circuit 8.

The allocation signal decoder 10 decodes the allocation signal, sends a write address for writing to the buffer memory 7 from the address vA23, including the trunk portion where the CH was not found, and writes as shown in FIG. 3(E). .

Next, this is read out from the address line 22 at the read address in the numerical order shown in FIG. 3(F) and assigned to the corresponding trunk. Noise is inserted in step 6.

In this way, the DSI device performs a call with a high utilization rate of the transmission path.

In this case, to eavesdrop on the voice signal, it is necessary to decode the above-mentioned assigned signal, but since this is constantly changing, eavesdropping is difficult, and it is currently not used much except for some international lines. There is no attempt to conceal audio signals transmitted through DSI devices, but if DSI devices become more common in the future, encryption will be necessary, but there is a problem that this method has not been proposed.

[Means for solving problems]

The problem described above is that the output channel assignment control circuit that assigns the signal of the input trunk where voice is detected to a channel of an empty transmission path encrypts the assignment signal, and the output channel assignment control circuit also encrypts the assignment signal. The encryption of the present invention is characterized in that a plurality of address conversion means are added to the address line to the buffer memory for time slot/node allocation of the frame of the road, and the plurality of address conversion means are switched to rungs in synchronization with this encryption. This problem can be solved by using the following method.

[Effect]

The present invention encrypts the assignment signal from the output channel assignment control circuit, and in synchronization with this encryption, randomly switches a plurality of address translation means by generating random numbers, etc., and changes the order of trunks assigned to the channels of the transmission path. By making the information random, encryption is performed with high secrecy.

〔Example〕

FIG. 1 is a block diagram of a DSI device according to an embodiment of the present invention, in which (A) shows the transmitting side and (B) shows the receiving side.

In the figure, 30 is an encoder, 31.35 is a random number generator, and 32.3
3, 36.37 is a selector, 34 is a decoder, 1-1 to 1
-N, 2-1~2-N, 3-1~3-N, 4-1~4-
N indicates a ROM, and the same reference numerals indicate the same functions throughout the drawings.

The difference between FIG. 1 and FIG. 2 is that the assignment signal from the output channel assignment control circuit 5 is encrypted and transmitted by an encoder 30 using, for example, DBS (data encryption standard), and the receiving side uses a decoder. 34 to obtain the original allocation signal and pass it to the allocation signal decoder 10, and on the transmitting side, the address '! For example, the write address shown in FIG. 3(A) from lA20 is changed from 1 to 2 in R0Ml-1. In ROM1-2, N types of conversion means are provided in N ROMs ROM1-1 to 1-N, such that 1 is converted to 3°...and in ROMI-N, 1 is converted to l+N, and from the address line 21. Figure 3 (C
), for example, in ROM2-1, 1 to 2. In ROM2-2, 1 is changed to 3,...ROM2-
For N, like converting l to 10N, ROM2-1 to 2-
N (7) N types of conversion means are provided in N (7) ROMs.

On the receiving side, the read address shown in FIG.
In the ROM 3-1, 2 is changed to 1 so that the audio signals are returned to their original order in accordance with the write address converted in . ROM
In 3-2, 3 is 1. ...For ROM3-N, N÷1 is 1
(N ROs of ROM'3-1 to 3-N
M is provided with N types of conversion means, and the write address for writing the audio signal in the order of the transmitted channels, including the trunk portion to which no CH is assigned, from the address line 23 is stored in the ROM 2-1 to ROM 2-1 on the transmitting side. ROM4-1 to restore the original order in accordance with the read address converted in 2-N.
So let's turn 2 into 1. In ROM4-2, 3 is set to 1. ...ROM4
-N, like converting N+1 to 1, ROM4-1 to 4
-N types of conversion means are provided in N ROMs,
Furthermore, random number generators 31 and 35 that generate the same random numbers are provided on the transmitting and receiving sides, respectively, and the encoders 30 and 35 are respectively provided on the transmitting and receiving sides. The random number generators 31 and 35 generate the same random number according to the cryptographic synchronization signals S and R of the decoders 34 and ', and the selector 3
For example, ROMl-1 and RO
M3-1. Corresponding ROMs such as ROM2-1 and ROM4-1 are selected, and the conversion means stored in these ROMs is used to write to and read from the buffer memory 2.7, and the input on the transmitting side is The point is that the receiving side sends the audio signal from the trunk to the corresponding trunk.

In this way, the assigned signal is encrypted on the transmission path, and the order of the trunks assigned to the CHs on the transmission path is further randomized, thereby indirectly performing high-level encryption of the audio signal.

Also, since the allocation signal only needs to be encrypted once for each ICH,
Selector 3-2.33, 36.37 only needs to be selected once per ICH, and can be done at a slower speed than encrypting the audio signal itself. This method makes it possible to encrypt things that could not be encrypted for this reason.

[Effects of the Invention] As explained in detail above, according to the present invention, there is an effect that a DSI device can be highly encrypted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DSI device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional DSI device, and FIG. 3 is a diagram of writing to the buffer memory 2.7 in the case of FIG. , readout, and transmission signals. In the figure, 1.8 is a delay circuit, 2.7 is a buffer memory, 3 is a multiplexing unit, 4 is an audio detection unit, 5 is an output channel assignment control circuit, 6 is a noise insertion unit, 9 is a separation unit, and 10 is a separation unit. Assignment signal decoding section, 30 is an encoder, 34 is a decoder, 32.33, 36.37 is a selector, 31.35 is a random number generation section, 1-1 to 1-N, 2-1 to 2-N, 3 -1~3-N, 4
-1 to 4-N indicate ROM. Kaya 2 groups (A)

Claims (1)

[Claims] In a digital speech interpolation device, an assignment signal from an output channel assignment control circuit that assigns a signal of an input trunk in which voice is detected to a channel of an empty transmission path is encrypted, and the output channel assignment control circuit also performs the output channel assignment control circuit. A plurality of address conversion means are added to the address line from the circuit to the buffer memory for time slot allocation of frames on the transmission line, and in synchronization with this encryption,
An encryption method characterized in that the plurality of address translation means are switched at random.