JPS61139175A - Conversion for video signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention provides an interlaced video signal by simultaneously generating two field signals and subsequent parallel/serial conversion and time compression of the corresponding scan line signals. A method for converting a video signal into a non-interlaced video signal with twice the number of scan lines, the method comprising: making the transmission of the converted video signal dependent on the image content for a stationary image area and a moving image area; Using and controlling a double line number video signal is formed from two successive fields of interlaced line signals for stationary image areas and one in each case for moving image areas. The present invention relates to a video signal conversion method in which scan lines missing from a field are extracted by interpolation.

The standard conversion of the video signal obtained in the prior art interlaced scanning system into a frame representation, that is, the standard conversion in which two temporally consecutive fields r are simultaneously reproduced on the monitor screen, is useful for detecting moving image areas. Requires. This motion detection can be performed using e.g. an increased image repetition frequency (75Hz, 10Hz) for further frame signal processing.
Q Hz), frame playback using a noise reduction device, and frame playback using a cross-color noise reduction method in the PAL standard.

In contrast to motion detection, which is used in interlaced playback, e.g. in connection with a noise reduction device, and is based on the formation of an image difference between two spatially identical fields 2, simultaneous Both image differences between two spatially identical fields as well as temporally and spatially displaced fields must be relevant for motion detection.

During the frame reproduction of an image scene scanned in an interlaced manner, motion causes a disturbing trailing blur, which appears in a comb-like structure at the vertically located edges of an object moving in the horizontal direction. Therefore, in moving image areas, two fields should not be combined into one frame. This is because, in this case, the two moving time phases of the subject are also reproduced at the same time. Therefore, one real field r in each case is interpolated into one composite frame. Depending on the control variable, dissolution occurs between frame playback and this field interpolation.

Problem to be Solved by the Invention Forming an image difference between two spatially identical field planes and using this difference signal as a control signal via a non-linear function, German Patent Publication No. 3233882 When using the motion detection method known from the above, it is still possible to avoid the above-mentioned motion-induced tails in the case of frame reproduction controlled adaptively to motion in a predetermined pattern, which has thin image structures that move intermittently. Drifting blur occurs.

It is therefore an object of the invention to generate a control signal which makes it possible, in a method of the type mentioned at the outset, to ensure that trailing flow pickets due to movements no longer occur.

Means for solving the problem In order to solve the above-mentioned problem, the invention provides that the two difference signals for generating the control signal are derived in each case from the two field signals.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Terminal 1 of the block circuit diagram of FIG. 1 is supplied with a video signal of conventional television standards (312.5 scan lines per field, 50 fields per second). The video signal is converted into a signal having 50 frames per second and C 625 scanning lines per field and is adapted to be displayed on the image screen 2 of the monitor 3 in a so-called frame display. The video signal to be converted is first fed to six field memories 1J4, 5.6 connected in series and delayed by one frame V period in each case. Now, for example, the first video signal
If the field of the cylinder 2 passes through all the field memories 4, 5.6 and is retrieved at the output of the third memory 6.
can be taken out by a second field at the output side of the memory 5. On the other hand, on the input side of the first memory 4, the fourth
The feel r or the actual feel V at that time is entered.

The output signals of field memories 4 and 5 are supplied to a video signal processing system via terminals 7 and 8. The video signal at terminal 7, delayed by one filter P period, is fed on the one hand to a first input of a parallel/serial converter 9 and on the other hand via an interpolating vertical low-pass filter 1 to a day delp circuit. supplied to one input side. At the same time, the video signal at the terminal 8 delayed by two field periods is sent to the day delp circuit 12.
is supplied to the other input side of the .

The output side of the dissolve circuit 12 is connected to the second input side of the parallel/serial converter 9. The dissolve circuit 12 is controlled as follows depending on the control signal supplied from the motion detector 13.

That is, in image areas that do not actually move, the signal taken out from the terminal 8 is supplied, and in image areas that move rapidly, either the scan line signal interpolated by the low-pass filter 11 or the signal of two locally adjacent scan lines is supplied. The planned sum signal is controlled to be supplied to the day delve circuit 12.

The field signals fed simultaneously to both inputs of the parallel/serial converter 9 are parallel/serial converted so that the simultaneously present information from two locally adjacent scanning lines is sequentially
However, it is read out twice as fast and supplied to the monitor 3.

That is, on the image screen 2 of the monitor 3, a frame picture having 625 scanning lines is played one after another within one field period, and the frame picture is composed of fields 1 and 2 or fields 2 and 3 or field 3 of the input video signal. and 4.

To generate a control signal, the motion detector 13 is simultaneously supplied with signals from four fields of input signals.

Difference signals are formed in subtraction circuits 14 and 15 from two spatially identical fields in each case. Since the sign of this difference signal of the motion detection reservoir is not important, the difference signal is supplied to value forming reservoir circuits 16 and 17, respectively. After value formation, these difference signals are each fed to the respective input of the adder circuit 18. The output total signal is processed by processing circuit 1.
9 is converted into a control signal with a non-linear characteristic curve and taken off at the output 20.

Two difference signals are formed with a spatial shift. This means that before the addition, the scan line is delayed using a transit time element 21, so that the addition of the undelayed signal and the delayed signal is obtained in the summing stage 22, and in the stage 23 the coefficient Multiply by 0.5 to obtain the evaluated value.

Another embodiment of the motion detector 13' is shown in FIG. The video signal to be converted is fed to terminal 1 and connected in series to two field memories 24.2.
5 delays a total of two field periods. Thereafter, field signals are taken out at terminals 7 and 8 and processed in the same way as in FIG.

In order to generate a control signal, the motion detector 13' is supplied with an actual input signal, a signal delayed by two field periods, a sixth field signal, and a first field signal. be done. a difference signal is formed from the sixth field signal and the first field signal using a subtraction circuit 26;
The difference signal is fed via a value forming circuit 27 to a processing circuit 28 with a non-linear characteristic curve.

Therefore, on the output side of this processing circuit 28, there are two.

Partial control signals can be extracted from the same field. This partial control signal is fed directly to the first input of the summing stage 31 on the one hand and via the third field memory 29 to the second input of the summing stage 31 on the other hand.

The two inputs of this summing stage 31 are therefore in each case simultaneously supplied with two different partial control signals 30 and 30'. For example, a first input is supplied with a control signal 30 taken from fields 2 and 4, and a second input is supplied with a control signal 30' taken from fields 1 and 3. The two partial control signals 30 and 30' are summed in a summing stage 31 to generate a control signal which is available at terminal 20.

This embodiment has the advantage that the memory capacity of the third field memory 29 can generally be smaller than the capacity of the field memory 24.25 for video signal delays. This is because the control signal must not be quantized with a word width as large as the video signal.

Furthermore, in this embodiment, still image reproduction of a moving scene can be realized very easily.

In the case of frame playback, the continuous information from the moving scene must also be stored. This problem involves the processing circuit 2 responding to a "still image playback" command during the field period.
By writing the output signal of the addition stage 31 into the field memory 29 instead of the output signal of the third field memory 29. Furthermore, selector switch 3
2 is switched to the position indicated by the dashed line.

After this field period has elapsed, any field)
) 24.25.29 is also blocked, and the stored information remains "until the still image playback J command is canceled, that is, until the selector switch 32 is switched to the F position again. Read repeatedly.

Instead of adding the partial control signals 30 and 30' derived from both difference signals, the two partial control signals may also be combined non-linearly. For this purpose, there are embodiments in which the larger amplitude value is selected in each case. FIG. 3 is a block circuit diagram corresponding to this. Both partial control signals 30 and 30' to be combined are fed to a comparator 33, which compares the amplitudes of the two signals.

According to the determination of which partial control signal has a larger amplitude value, the larger partial control signal is selected as the control signal via the changeover switch 34 and taken out at the output terminal 20.

Effects of the Invention According to the method of the present invention, the moving phase of the object in all 14 fields is detected when the two difference signals are added, and therefore it is possible to prevent tailing and flow blurring due to movement during frame playback. has advantages.

[Brief explanation of drawings]

1 is a block circuit diagram of an apparatus for carrying out the method of the invention, FIG. 2 is a block circuit diagram of another embodiment of a motion detector, and FIG. FIG. 3 is a block circuit diagram of a partial modification of the circuit of FIG. 4.5.6...Field memory, 11...Interpolating vertical low-pass filter, 12...Dissolve circuit, 13...
・Motion detector, 14.15...Subtraction stage, 16°17・
... Value forming circuit, 19... Processing circuit, 21... Scanning line delay circuit, 24, 25. 29... Field memory, 26... Subtraction stage, 27... - Value forming unit, 28...・・・
Processing circuit, 30... Addition stage, 32... Changeover switch, 33... Comparator

Claims (1)

[Claims] 1. Generating two field signals simultaneously, converting the interlaced video signal by a factor of 2 to non-interlaced by subsequent parallel/serial conversion and time compression of the corresponding scan line signal. A method for converting a video signal into a video signal with a number of scanning lines of The number of scan lines of the video signal is formed from two consecutively occurring fields of an interlaced scan line signal for stationary image areas, and the interpolation of scan lines missing from one field in each case for moving image areas. A video signal conversion method characterized in that two difference signals for generating a control signal are each derived and extracted from two field signals. 2. The video signal conversion method according to claim 1, wherein a difference signal is extracted from two spatially equal field signals. 3. Claims in which one difference signal is taken out from two odd-numbered field signals, the other difference signal is taken out from two even-numbered field signals, and after forming a value, the two difference signals are added. The video signal conversion method according to item 2. 4. The video signal conversion method according to claim 3, wherein the resultant signal obtained by adding the two difference signals is converted into a control signal by non-linear evaluation. 5. The method of claim 3, wherein one of the difference signals is used to perform a vertical average over two scan lines before summing. 6. The video signal conversion method according to claim 3, wherein the difference signal after value formation is converted into a partial control signal by non-linear evaluation before being added. 7. The video signal conversion method according to claim 6, wherein the partial control signal extracted from the difference signal is delayed by one field, and then added to the partial control signal extracted from another difference signal and converted into a control signal.