KR970002696B1 - Television standard converter - Google Patents

Abstract

None.

Description

TV system converter

1 is a simplified schematic block diagram of a television system according to the present invention.

2 is a schematic block diagram of a first embodiment of a television system according to the present invention;

3 is a schematic block diagram of a second embodiment of a television system according to the present invention;

4 is a detailed block diagram of a first embodiment of a television system according to the present invention.

5 is a detailed block diagram of a second embodiment of a television system according to the present invention.

6 is a more detailed block diagram of the embodiment of FIG.

7 is a time chart for explaining the operation of FIG.

8 is a more detailed block diagram of the embodiment of FIG.

9 is a time chart for explaining the operation of FIG.

10 is a partial detailed block diagram of the embodiment of FIG.

11 is a time chart for explaining the operation of FIG.

12 is a partial detailed block diagram of the embodiment of FIG.

* Explanation of symbols for main parts of the drawings

1, 1Y, 1C: Interpolator 2: Motion Analyzer

11, 11Y, 11C, 22: 4-field TBC 16, 16Y, 16C, 43: Shift register

17, 17Y, 17C, 42: Delay 18, 18Y, 18C, 21: 2 Field TBC

31: Demultiplexer 34: Multiplexer

36: vector filter 37: vector calculator

38: vector processor 39: subpixel motion evaluator

40: vector reducer 41: vector selector

61, 71, 81: Line counter 82: Field counter

88: scaler

The present invention relates to a television based converter and a slow motion processor.

International television program exchanges require different types of televisions, such as the PAL system at 625 lines per second used in the UK and the NTSC system at 60 fields per second at 525 lines used in the United States. to be.

Therefore, many type converters have been proposed in the past. The best known is ACE (Advanced Conversion Technology), developed by British Broadcasting Corporation. The basic operation principle of this ACE is to extract a predetermined interpolation sample line by line from the input digital television signal to form an output digital television signal. Interpolation uses four consecutive horizontal scan lines of the input television signal spatially and four continuous fields of the input television signal in time. Therefore, each sample from the 16 input television signal lines is multiplied by a weighting coefficient to extract the output television signal for each line.

For ACE, R. N. Robinson and G. J. Cooper, published in British Patent Specification GB-A-2 059 712 and pages 11 to 13 of the January 1982 issue of Television, a journal of the Royal Television Association. This paper is presented in detail in the four-field digital converter of the 80s.

ACE has good performance but the device itself is very large. To solve this problem, the inventors of the present application have already received an input digital television signal and extract an array of 16 lines from this signal, each array having four consecutive lines from four respective consecutive fields of the input television signal. A television type converter with three field memory and four four line memories is proposed. The weighting coefficient memory stores 16 sets of weighting coefficients, each set corresponding to the temporal and spatial position of each line of the output digital television signal in a different manner with respect to the 16 input television signals. Two interpolation filters multiply sample values from each of the sixteen input television signal lines by each corresponding weighting coefficient of the weighting coefficient set and sum them to extract the output television signal line by line, and the four output field memories extract the Receive and store output television signal lines. When the output television signal has more lines than the input television signal, a 45-line memory is inserted between one interpolation filter and the output field memory to store the extracted additional lines. More details are described in British patent specification GB-A-2 140 644.

The performance of this type of transducer using vertical and temporal interpolation techniques represents a compromise between the resulting blobs and maintains good motion picture quality and good vertical resolution but is expensive. The former results in post filtering to prevent interference effects, while the latter results in the elimination of the interference of a causal two-dimensional repeating sample structure.

It is an object of the present invention to provide an improved television system converter.

Another object of the present invention is to provide an improved television system converter for converting 625 lines of 50 fields per second to 525 lines of 60 fields per second.

Another object of the present invention is to provide an improved television system converter for converting 525 lines 60 fields per second to 625 lines 50 fields per second.

Another object of the present invention is to provide an improved slow motion processor.

According to the present invention, a television system converter includes means for analyzing the operation between continuous fields of an input television signal of an arbitrary television system, means for aligning the fields to effectively reproduce still images, and converting the still images to other televisions. Means for extracting a predetermined output television signal of the system.

A television system for converting 625-line 50 fields into 525-line 60 fields according to the present invention includes a four-field time base corrector for receiving an input digital television signal of 625 line 50 fields and an output of the time axis corrector. A predetermined 525 line 60 based on a motion analyzer for analyzing the operation of the television signal, a shift register attached to the output of the time base corrector, image motion data extracted by the motion analyzer, and a sample extracted from the shift register. An interpolator for extracting a sample of a digital television output signal of a field, and a two-field time base corrector for combining the extracted samples to form the output television signal.

A television system for converting 525 line 60 fields into 625 line 50 fields according to the present invention includes a two-field time base compensator for receiving an input digital television signal of 525 line 60 fields and an output of the time base compensator. A predetermined 625-line 50 based on a motion analyzer for analyzing the operation of the television signal, a shift register attached to the output of the time base corrector, image motion data extracted by the motion analyzer and a sample extracted from the shift register. An interpolator for extracting a sample of a digital television output signal of a field, and a four-field time base corrector for combining the extracted samples to form the output television signal.

The slow motion processor according to the present invention includes an input circuit for receiving an input digital television signal, an operation analyzer for analyzing the operation of the input digital television signal, a shift register for holding another continuous field of the input television signal; An interpolator for extracting a sample of a predetermined slow motion output digital television signal based on the image motion data extracted by the motion analyzer and the slow motion degree of the sample extracted from the shift register, and combining the extracted sample And a two-field time base corrector for forming the slow motion output television signal.

The above objects, features and advantages of the present invention will be described in more detail with reference to the embodiments illustrated in the accompanying drawings.

The mode converter eliminates judder by maintaining vertical resolution and compensating for motion between fields. The operation between successive fields is effectively analyzed. These fields are arranged to reproduce still images, and the conversion is performed. As a result, the vertical resolution can be maintained.

The mode converter is divided into two parts. One part is the well known analogue type converter which performs vertical and time interpolation to convert the 625/50 and 525/60 television types. At this time, the vertical resolution is maintained but an output with an abnormal vibration effect is generated. Four fields of the input digital television signal used in the conversion process to eliminate the anomalous vibration effect are arranged under the control of the motion vector generated from the motion analyzer forming the modal converter second part.

1 is a very simple block diagram.

For example, a video portion of an input digital television signal of any one type obtained by sampling an analog television signal at 13.5 MHz is supplied to the interpolator 1, and from this interpolator, a predetermined output television signal of a different method than that described above. The video part of is obtained. The motion analyzer 2 receives the video brightness, extracts the motion vector, and supplies data to reproduce the motion between successive fields of the input television signal to control the operation of the interpolator 1. The interpolator 1 operates in the same way as the corresponding part of the known mode converter, for example as described above. However, it also includes means for arranging four fields used for interpolation under the control of the motion vector.

Positioning of the four fields is carried out in two steps. In the first step, the address of the variable delay element associated with each field is changed to move the image to the laborious line or sample. In the second step, use two horizontal and vertical interpolation techniques to place within ± 1/8 of one sample or ± 1/16 of one line. Even if there is no operation, the above two techniques are used to perform the line conversion.

The vertical interpolator has four tabs per field, effectively applying a vertical filter of eight tabs for still images. The 8-tap interpolator maintains good vertical resolution with minimal distortion. In a horizontal interpolator, this is not a problem, so a four-tap horizontal filter can be used, but a two-tap horizontal filter is used.

The time interpolator is used when a normal operation or a detectable motion vector that enables interpolation of sensitive changes cannot be detected, in which case the interpolator 1 switches to a normal standard mode conversion operation in which no relocation of the image occurs. You have to.

When converting from a high field to a low field, the input field is interpolated so that interpolated fields are temporarily missing without degrading any operation. All interpolation is performed at the input field rate and delivered to the time base corrector, which develops the field generated over a predetermined time for the output scheme.

This action is necessary when converting from 525/60 to 625/50. However, it is clear that 625 lines should be generated when there are only 525 lines in the input signal.

To overcome the line-number conversion problem, a second time base corrector is used on the input side to generate a signal with 585 lines at 60 Hz. The 585 line format may include all active picture information in the 625 line format. A line without video information is generated by the first time base corrector. At this time, the interpolator memory is frozen, as a result of which an additional interpolation line can be generated from the same line used to generate the preceding output line. This method interpolates from the original 525 lines to 625 lines.

The reason for choosing the 585/60 format will now be described in detail. The 625-line screen contains 288 active lines in each field, and 720 samples at a sampling rate of 13.5MHz on each horizontal line. The circuits of the embodiments of FIGS. 4 and 5 use a method that causes the screen to be shifted horizontally by ± 24 samples. This requires horizontal blanking of at least 48 samples. Therefore, the total number of sample positions required for the field is as follows.

(720 + 48) × 288 = 221184

The system uses a clock of 13.5 MHz and the obvious advantage is the number of clock cycles in the 60 Hz period (exactly 59.94 Hz period) in this case 225225.

If 576 lines of data are required in one frame, the number of horizontal samples is 782.03125. This number contains enough (720 + 48) samples, but a single sample means that the structure is non-orthogonal to the axis between the lines. This creates a significant difficulty in the design of the modal converter. Thus, the predetermined number of lines gradually increases from 576 until the total number of samples present in each line is actually 770.

The only format that forms a right angle structure is the 585/60 format, which also provides vertical blanking of 4 lines in the first field and 5 lines in the second field and 50 blanks of horizontal blanking.

In the 625/50 vs. 625/50 slow mode of operation, the storage of the 625 format active video within a 60 Hz period is not required and interpolation and other processing is performed in the standard 625/50 format.

When converted from low field to high field, the input time base corrector is required to produce the video stream at the output rate. This is done by repeating the input fields. When a repeating field occurs, all interpolator memory is frozen, interpolating the same input field used to generate the preceding output field.

If this technique is not used, two sets of interpolators and moving detectors are needed to compensate for the lack of fields.

The operation is performed when converting from 625/50 to 525/60. The intermediate format of 585/60 is adopted so that there are 625 lines in 60 field periods per second. Some interpolation lines are not needed because only 525 to 525 should be generated during this process. Thus, on the output side, a time base corrector is needed to produce the 525/60 format.

The predetermined interpolation amount is determined by comparing the input and output sync pulse phases. As noted above, motion analysis is performed on the brightness of the input video. The method used includes a number of steps to reach a single motion vector for each pixel. Motion is detected within a range of ± 24 pixels horizontally and ± 8 (field rate) vertically.

In the first step, the screen motion at points on the screen 16 pixels horizontally and 8 lines vertically, is determined using a block matching technique. The original motion vector of the field is calculated every 16th sample and every 8 lines. Each of these points is at the center of the search block. Conceptually, each time the sum of the differences between two fields occurs in the area of the search block, each block in the next field is scanned +/- 24 samples horizontally by +24 samples and vertically. The minimum overall difference represents the direction in which the subject moves at that point.

In practice, the technique is applied at each individual step, which significantly reduces the amount of hardware and complexity. In other words,

Step 1

The minimum difference is tested at three positions: the center position of the block, the left position of 16 samples, and the right position of 16 samples.

Step 2; It starts from the said point.

The minimum difference at 9 positions symmetrically distributed with respect to the starting point is tested at the stage of 8 samples or lines.

Step 3; It starts from the said point.

Nine minimum symmetrical differences are tested with respect to the starting point at the stage of four samples or lines.

Step 4; It starts from the said point.

Nine minimum symmetrical differences are tested for the starting point in two sample or line steps.

Step 5; It starts from the said point.

The minimum difference of nine positions symmetrically distributed with respect to the starting point is tested in one sample or line of steps.

Step 6

After step 5, the motion of the subject is detected at the nearest pixel. A more accurate vector value can be realized by step 6 of adjusting the vertical vector value by comparing the difference created at the final position indicated by step 5 with the two differences between the upper and lower sides, and by adjusting the horizontal vector value by comparing the two differences between the left and right. .

The above technique depends on the correlation between the reference search block and the image data of the similar block (search position) on the next field. In step 5, there may be an actual operation on the order of half a pixel than that detected, and even if the correct correlation cannot be obtained, the best correlation is required at this point. To this end, the picture can be filtered both horizontally and vertically by a Gaussian filter that is attenuated by +6 dB at 1/2 Nyquist frequency.

Similarly, for step 4, the screen can be filtered with 6 dB attenuation at 1/4 Nyquist frequency, which allows 1 pixel error in detection.

Step 3 uses a 6dB attenuated filtered picture at 1/8 Nyquist frequency, which allows for 2 pixel error.

Step 2 uses a filtered picture with 6dB attenuation at 1/16 Nyquist frequency allowing for 4 pixel error.

Step 1 uses a 6dB attenuated filtered picture at 1/32 Nyquist frequency, which allows for 8 pixel error.

In addition, since the screen has been filtered in large quantities during steps 1,2,3 and 4, the number of samples can be reduced in half, for example, which further reduces the number of calculations and the amount of predetermined hardware.

Valid search block sizes are 16 lines and 48 samples. Large search blocks are needed to accurately detect the motion of a large planar region. The central part of the planar area is not important because the pixel value of the point does not change from one field to the next, but the edge of the subject is very important. If motion detection is limited to ± 24 samples horizontally and ± 8 lines vertically, the size of the search block is the minimum size that ensures accurate motion detection.

In the embodiment, the luminance video input to the operation analyzer 2 according to the conversion mode is in various forms of 585 lines / 60 fields per second. This consists of a repeating field for a 625 line input or a repeating line for a 525 line input. The input also contains both field polarities. The first process guarantees single field polarity and continuity of data with respect to the motion prediction process. This is done by interpolation on the input data by the vector interface to maintain horizontal filtering and continuity to help continuous motion detection / correlation.

Individual outputs from this circuit are passed through a motion prediction vector filter and a motion detection field memory / vector selector. As described above, the output of the vector interface is spatially continuous and single field polar data. The output to the field memory / vector selector depends on the input and output modes. In some modes it is continuous and in others it contains repeating lines / fields. The vector filter and the vector calculator perform the above steps.

Various stages of processing are performed by the vector calculator and the vector processor. The vector calculator executes steps 1 to 5 and the vector processor executes step 6. In addition, the vector processor executes the second step as follows when the operation is expected.

For each 8x16 block, four are selected from seven motion vectors, where seven motion vectors are one for the particular block and six for the six most labored blocks.

Also, the vector processor determines four most common motion vectors through the entire input field, which is called a modal motion vector. The modal motion vector is preferentially used in the border region near the edge of the field where it is virtually impossible to calculate any local motion vector. Also, if more than one local motion vector is the same, they are replaced with all motion vectors.

In the next step of motion detection, for each pixel, four motion vectors are tested by generating a difference between the positions extrapolated to fields 0 through 1. During the transformation, interpolation is required between two fields, field 0 and field 1. Therefore, the motion vector generated between the two fields is regarded as the most representative motion. Four motion vectors are used from these two fields. To determine which is the correct motion vector, the pixel from field 0 is compared with the pixel from field 1 so that the pixel to be generated using that motion vector is from field 0 and the pixel is executed by field 1. To decide. Mathematically, if we set the positions x, y, z (where x is the horizontal position, y is the vertical position, z is the time position between field 0 and field 1), the pixels used for the comparison are as follows. Field 0 is when z = 0 and field 1 is at z = 1.

Pixels from field 0

x ⁰ = xV _h ^* Z

y ⁰ = yV _v ^* Z

Pixels from field 1

x ¹ = x + (1-z) V _h

y ¹ = y + (1-z) V _v

V _h = horizontal component of the vector

V _v = vertical component of the vector

For each motion vector, a modulus of the difference between the pixels indicated in field 0 and field 1 is generated. Assume that the minimum difference represents the correct motion vector as the first evaluation value. If multiple motion vectors produce very similar differences, these motion vectors are tested again using a comparison between fields -1 and 0.

Pixels from field -1

x ^-1 = x- (1-z) V _h

y ^-1 = y- (1-z) V _v

The minimum difference of the remaining motion vectors generated by the second test is considered to reproduce the motion vectors most accurately.

If multiple motion vectors again have similar differences, there is an option to assume no motion. If only the horizontal component changes and the vertical component does not change, only the horizontal component is set to zero and the vertical component is kept at the detection value. If only the vertical component changes, the horizontal component is maintained and only the vertical component is set to zero. If the pixel difference is selected too large, you have the option to set all motion vectors to zero in both directions.

After all pixels have been specified as motion vectors, the last step is applied. Here, the motion of each pixel is tracked from one field to the next, and a cyclic filter is applied to the motion vector value. This removes noise and evaluation errors of small motion and smooths the trajectory of the motion vector.

There are two ways to track the motion of a pixel. First, the motion vector for the pixel in field t is used to indicate the pixel in field t + 1. The motion vector determined for the pixel in field t + 1 is cyclically filtered to form the final motion vector for the pixel in field t + 1. Secondly, the motion vector for the pixel of the predetermined field t is used to indicate the pixel of the field t-1. The motion vector from this pixel is cyclically filtered as the motion vector for the given pixel to form the final motion vector for the given pixel in field t.

In either case, the final output is one motion vector for each pixel, which is passed from the motion analyzer to the interpolator used to arrange the four fields used for the transform method.

A first embodiment of a method converter for converting an input television signal of digital 625 line 50 fields into an output television signal of digital 525 line 60 fields will be described with reference to FIG. 2, which is a schematic block diagram of the method converter. .

50 fields of video are supplied to a four-field memory time base corrector (TBC) 11 at a sample rate of 13.5 MHz. This TBC 11 repeats the field, and the output becomes 60 fields. The control of the TBC 11 to repeat the field is derived from an input field sync pulse and a predetermined output sync pulse. The comparison of the synchronous pulses provides a temporal offset phenomenon indicating the amount of time interpolation required at the output of the TBC 11 and a smoothing operation at 60 fields is obtained.

In this way a line conversion from 625 to 525 is required when converting from 50 fields to 60 fields. Thus, the original 625 information lines in 60 fields need to be continued and they form an interpolation line.

The embodiment used an intermediate scheme that could include all active vertical information of 60 to 50 fields. This intermediate scheme also contains all of the active line information orthogonally arranged line by line using the original 13.5 MHz sample rate.

The intermediate scheme as described above for all conditions uses a 585 line format in 60 fields. When sampled at 13.5MHz, each line in this format is exactly 770 samples. Thus, 585 lines are sufficient to contain 576 active lines in a 625 line format in 60 fields. The width of the active line is only 720 samples, resulting in 50 samples of horizontal blanking.

The linear motion compensated interpolator 1 has a format of 585 lines from the TBC 11 via four field memories 12, 13, 14 and 15 arranged as a time shift register 16. Generate a signal. When the output of the TBC 11 is frozen, the shift register 16 is also frozen during the repeating field so that four consecutive individual input fields are always present in the shift register 16. At this time, the shift register 16 is used as a temporal tap for the interpolator 1.

Direct data can be supplied from the output of the TBC 11 to the motion analyzer 2 to generate a motion vector. In practice, a frame delay 17 is required between the TBC 11 and the shift register 16 to allow time for processing the motion vector. Therefore, freezing of the shift register 16 must be delayed by one frame.

Each temporal tap forms four line taps at locations along the motion vector, so that a two-dimensional filter can be used to perform interpolation. The interpolated screen includes 576 active lines, and as a result, an accurate screen is obtained whenever the sixth line falls from one field. The left 484 lines form the active screen portion of the 525-line format. To subtract lines in this way, the output from interpolator 1 is fed to a two-field TBC 18. The TBC 18 writes all 576/2 lines, but reads out only the necessary 484/2 lines to generate a predetermined output television signal.

The above embodiment can be easily modified to form a slow motion processor which results in a good motion description. However, it is not necessary to use a vertical interpolator for line number conversion.

When converting from 50 fields to 60 fields, the field is temporarily repeated, while in slow operation, the field is repeated as much as the input field is repeated. Since the repetitive field is not recorded in the shift register 16, the shift register includes individual consecutive fields. In fact, if the video tape recorder plays back without any interpolation of its own, the original interface structure is maintained such that a full resolution screen is played. The predetermined temporal offset is calculated by comparing the rate at which new fields are received with actual field rate pulses of 50 or 60 fields per second. To determine the temporal offset in this way, the system needs an available signal that represents the actual field polarity of the field that is repeatedly reproduced. Vertical interpolators always produce the required field polarity at the output.

As a result, the TBC 11 is not substantially necessary for slow operation but simplifies the frame structure and the system structure.

Fig. 3 shows a schematic block diagram of the type converter of the second embodiment, which converts a television signal of 60 input fields of an input digital 525 line into a television signal of 50 fields of an output digital 625 lines. In this case, all input data need to be obtained continuously in interpolation. In this embodiment, it is impossible to convert to 50 fields before the interpolator 1. However, the input data contains only 484 active lines and the interpolator 1 should generate 575 lines. Thus, the two-field TBC 21 is placed in front of the scheme converter to provide the necessary time slots for the conversion of 484 lines to 576 lines.

The original continuous line structure is written in the TBC 21, but is read in a 585 line manner with the sixth line blanked. The interpolator 1 freezes its line memory during the blank input line to generate a continuous picture at an output line rate and generates a predetermined additional line at the output to ensure that a spatially accurate picture is produced. The predetermined temporal offset is detected and applied as in the first embodiment, so that motion smoothing remains even though interpolation is performed so that the field falls out in time. The field is missing so that 60 fields are converted to 50 fields. Dropping of the field is achieved by using a four-field TBC 22 at the output.

Referring to the detailed block diagram of FIG. 4, a first embodiment of a system converter for converting a television signal of 50 input digital 625 lines and 50 fields into a television signal of 60 output digital 525 lines will be described. The same reference numerals as used in FIG. 2 were used.

The demultiplexer 31 is supplied with 50 fields of input video, i.e., CCIR 601 data, at a sample rate of 13.5 MHz, and the demultiplexer 31 separates the data into luminance component Y, sync component SYNC, and chroma component UV. Luminance component Y is supplied to four-field luminance (TBC) 11Y, and chromaticity component UV is supplied to four-field luminance TBC 11C. The synchronization signal SYNC is supplied to the controller 32 along with an input field polarity signal from an external input and an output synchronization reference signal from another external input.

The luminance data D from the luminance TBC 11Y is supplied to the luminance time shift register 16Y having four field memories FS 12Y, 13Y, 14Y, and 15Y through the processing compensation delay unit 17Y. . The luminance TBC 11Y also supplies a temporal freeze signal F to the shift register 16Y through the delay 17Y. The chromaticity TBC 11C supplies the chromaticity data D to the chromaticity time shift register 16C having four field memories 12C, 13C, 14C, and 15C through the process compensation delay 17C. Chromaticity TBC 11C also supplies a temporal freeze signal to shift register 16C via delay 17C. The luminance interpolator 1Y that receives input from each field memory 12Y, 13Y, 14Y, 15Y is associated with a shift register 16Y. The output of the luminance interpolator 1Y is supplied to the two-field luminance TBC 18Y. A chroma interpolator 1C that receives inputs from each field memory 12C, 13C, 14C, 15C is associated with a shift register 16C. The output of the chroma interpolator 1C is supplied to the two-field chromaticity TBC 18C. The output of the luminance TBC 18Y and the output of the chromaticity TBC 18C are supplied to the multiplexer 34, which multiplies the luminance component Y and the chromatic component component UV to output in the form of a television signal of digital 525 line 60 fields CCIR 601 Supply the data.

The controller 32 supplies the control signal C to the luminance TBC 11Y and the chromaticity TBC 11C. The controller 32 also supplies a control signal to the luminance TBC 18Y and the chromaticity TBC 11C. It also supplies an interpolation control signal IC to the luminance interpolator 1L and the chroma interpolator 1C.

Only luminance data supplied by the luminance TBC 11Y is supplied to the operation analyzer 2 shown in the upper portion of FIG.

The operation analyzer 2 has a vector interface 35 to which luminance data from the luminance TBC 11Y and interpolation control signals from the controller 32 are supplied together. The vector interface 35 supplies the interpolated data in 625 lines to the vector filter 36 and the vector calculator 37 which perform the above-described operation evaluation. The output of the vector calculator 37 is supplied to the mode motion vector processor 38 and the subpixel motion evaluator 39. The motion vector processor 38 supplies four outputs, and the subpixel motion evaluator 39 supplies one output to the motion vector reducer 40, and the four outputs of this motion vector reducer are The vector selector 41 is supplied.

The vector interface 35 also supplies the interpolated data in even fields to the processing compensation delay 42, which is supplied with the received interpolation control signal and the time freeze signal generated at the vector interface 35. The data from the delay 42 is supplied to a time shift register 43 with three field memories 44, 45 and 46, which supply a data output to the vector selector 41, respectively. The delay unit 42 supplies an interpolation control signal to the vector selector 41, the vector selector supplies the selected motion vector to the cyclic motion vector filter 47, and the motion vector data output from the motion vector filter is luminance interpolated. To 1Y and chroma interpolator 1C.

Since the operation analyzer 2 has described in detail how to extract the motion vector data, the operation of the elements 35 to 43 and 47 will be briefly described.

The vector interface 35 receives the luminance data from the luminance TBC 11Y and the interpolation control signal from the controller 32. This feeds the 625 line data contained in the 585/60 format to the vector filter 36. This also supplies data to the delay 42. These data must contain the same line-type display as the required output normally contained within the 585/60 format. Each field of interpolation data must be even.

The vector filter 36 generates the filtered screen data required in steps 1 to 5 of the motion detection described above. The filtered picture data is supplied to the vector calculator 37 in a reduced form of samples.

The vector calculator 37 processes the filtered and sample reduced data from the vector filter 36 using the algorithm described in steps 1 to 5 of motion detection described above. The process is basically a two dimensional binary search of motion detection for pixel / line resolution. For each field, 1200 motion vectors are generated and supplied to the modal vector processor 38 and the subpixel motion evaluator 39. It also supplies the subpixel motion evaluator 39 with a weighted absolute difference (WAD) value as calculated in step 5 above. A detailed description of the WAD calculations is described in the paper Improved Image Coding of IEEE Procedures by Mooseman et al. In April 1985. The minimum specific WAD value in step 5 of motion detection provides a figure of merit (FOM).

The vector processor 38 calculates the four best common motion vectors detected in each field and supplies them to the vector reducer 40.

The subpixel motion evaluator 39 receives the WAD value together with the motion vector from the vector calculator 37. From this, the subpixel movement to be attached to the motion vector value is evaluated. Using each motion vector, the corresponding final WAD value is supplied to the vector reducer 40.

The vector reducer 40 receives motion vectors from the subpixel motion evaluator 39 and the vector processor 38. For each motion vector from the subpixel motion evaluator 39, the six motion vectors nearest to it are grouped together. Eleven are selected for each motion vector. The reduction process selects four motion vectors from eleven to supply to the vector selector 41.

The vector reducer 40 supplies four representative motion vectors to the vector selector 41 for 16 pixel-to-eight line blocks of the screen. By comparing the pixels on the three fields, the vector selector 41 selects the best one motion vector for each pixel on the screen. The selected motion vector is supplied to a motion vector filter 47.

The delay 42 delays by one frame of 21 lines or less to compensate for other delays in the system.

The time shift register 43 stores and supplies three fields of data used by the vector selector 41.

The motion vector filter 47 tracks the motion vector from one field to another, and combines the motion vectors of another field to filter the motion vectors and reduce motion detection errors. The output of the motion vector filter 47 is supplied to the luminance and chroma interpolators 1Y and 1 (C) to control the arrangement of the field data.

Slow motion processors of the same hardware may be used for 625/50 or 525/50 television signals. In all cases, the controller 32 determines what operation is required by recognizing the input / output method from the input / output field synchronization signal. In slow operation, the input field polarity is used.

5 shows a system converter of the second embodiment, and illustrates a system converter for converting a television signal of 60 input fields of an input digital 525 line into a television signal of 50 fields of an output digital 625 lines. The same reference numerals are used for the third diagram.

The second embodiment is somewhat different from the first embodiment shown in FIG. In other words, the luminance TBC 11Y and 18Y are interchanged with each other, and the chromaticity TBC 11C and 18C are also interchanged with each other. No temporal freeze signal is required. Except for the above, the operation and form of the second embodiment are the same as those of the first embodiment.

In both embodiments, the controller 32 has the following functions. That is, it controls the writing and reading of the TBCs 11Y and 11C, 18Y and 18C, generates a number of temporal offsets, generates a temporal freeze signal as in the case of the first embodiment, and controls vertical interpolation. Generate an offset number with the signal.

The two-field luminance and chromaticity TBCs 18Y and 18C always switch between field memories at the end of the 60 Hz field. However, the operation of the four-field luminance and chromaticity TBCs 11Y and 11C depends on the operation mode, and in fact, the control of the luminance and chromaticity TBCs 11Y and 11C is determined from the input / output field synchronization signal.

With reference to FIGS. 6 and 7, temporal offset signal extraction in the case of the conversion from 525/60 to 625/50 will be described.

In FIG. 6, the controller 32 is shown to include a line counter 61, first and second latches 62 and 63. The line clock signal is supplied to the clock terminal of the line counter 61, and the input field synchronization signal is supplied to the reset terminal of the line counter 61 and the clock terminal of the second latch 63.

The output field synchronization signal is supplied to the clock terminal of the first latch 62. The output of the line counter 61 is supplied to the input of the first latch 62, and the output of the first latch is the output of the second latch 63. The temporal offset signals are luminance and chromaticity shift registers 11Y and 11C. ), (18Y) and (18C).

7A and 7B show input and output field synchronization signals, respectively. FIG. 7C shows the output of line counter 61 counting from 0 to 524. FIG. 7d and 7e show the output of the first and second latches 62 and 63, respectively. By latching the counter 61, the input field period is determined. The temporal shift value tn represents the position between two input fields where the output field should be interpolated so that continuous operation occurs when the hatched field shown in FIG. 7A is left out. Thus, fields using the temporal offset shown by hatching in FIG. 7E are missing. As can be seen with reference to FIGS. 7A and 7B, the missing field does not have a new temporal shift associated with it. The field to be missed (arrow) is indicated in the next circuit by a temporal freeze signal.

8 and 9, the extraction of the temporal offset signal in the case of the conversion from 625/50 to 525/60 will be described.

In FIG. 8, the controller 32 is shown to include a line counter 71 and a latch 72. The line clock signal is supplied to the clock terminal of the line counter 71, and the input field synchronization signal is supplied to the reset terminal of the line counter 71. The output field synchronizing signal is supplied to the clock terminal of the latch 72. The output of the line counter 71 is supplied to the input of the latch 72, and the temporal offset signal which is the output of the latch is supplied to the luminance and chromaticity shift registers 11Y, 11C, 18Y, and 18C.

9A and 9B show input and output field synchronization signals, respectively. 9C shows the output of line counter 71 repeatedly counting from 0 to 624. 9d illustrates the output of latch 72. By latching the counter 71, the input field period is determined. Therefore, the temporal shift value tn represents the position between two input fields where the output field should be interpolated so that continuous operation occurs when the hatched field is repeated. The repetition field is a field with two temporal shift values associated with it. The field to be repeated (arrow) is indicated in the next circuit by a temporal freeze signal.

In the case of slow motion from 525/60 to 525/60 or from 625/50 to 625/50, the generation of the temporal offset signal is the same and will be described with reference to FIGS. 10 and 11.

In FIG. 10, the controller 32 includes a line counter 81, a field counter 82, first to fourth latches 83 to 86, an exclusive OR gate 87, and a scaler 88. It is shown as doing. The input field synchronization signal is supplied to the clock terminal of the first latch 83, the clock enable terminal of the field counter 82, and the second reset terminal of the line counter 81. The input field polarity signal is supplied with the output of the first latch 84 to the second input of the gate 87, and the output of the gate is the first reset terminal of the line counter 81 and the reset of the field counter 82. The set terminal and the clock terminal of the third latch 85 forming the speed detector latch are supplied. The line clock signal is supplied to the clock terminal of the second latch 84 and the clock terminals of the line counter 81 and the field counter 82. The output of the line counter 81 is supplied to the input terminal of the scaler 88, and the output of the field counter 82 is supplied to the input terminal of the third latch 85 and the offset input terminal of the scaler 88. The output field synchronization signal is supplied to the clock terminal of the fourth latch 86. The output of the third latch 85 is supplied to the scale factor terminal of the scaler 88, the output of the scaler is supplied to the fourth latch 86, and the output of the fourth latch becomes a temporal offset signal.

11A and 11B show an input field synchronization signal and an input field polarity signal, respectively. Fig. 11C also shows an input field synchronizing signal and Fig. 11d shows an output field synchronizing signal. 11E and 11F show the operation of the field counter 82 and the line counter 81 to count fields and lines from 0 to N. FIG. 11G shows the output of the fourth latch 86 which is a time offset signal. Figure 11H shows a time freeze signal (active when low), and the hatched field using the time offset as indicated by the arrow is a repetition of the preceding field used as the temporal offset t1.

To generate a time freeze signal, the controller 32 shown in FIG. 12 includes a synchronous RS flip-flop 91, latch 92, inverter 93, and AND gate 94. An output field synchronizing signal is supplied to one input of the flip-flop 91, the input of the inverter 93, and the clock enable terminal of the latch 92. An input field synchronization signal is supplied to the other input of the flip-flop 91, and a line clock signal is supplied to the clock terminals of the flip-flop 91 and the latch 92. The output of flip-flop 91 is supplied to one input of gate 94, and receives the output of inverter 93 at the other input of this gate. The output of the gate 94 is supplied to the input of the latch 92 and the output of this latch generates a time freeze signal. This circuit operates to cause freezing if one or more output field sync pulses follow the input field sync pulses.

Finally, referring back to FIG. 4 again, the generation of the vertical offset by the controller 32 will be described. The same address generator for reading data supplied from the luminance TBC 11Y to the luminance interpolator 1Y and the operation analyzer 2 addresses the EPROM, where necessary, if necessary, the number of vertical offsets along with the vertical freezing signal. (In the apparatus used to convert from 525/60 to 625/50 in FIG. 5, the read address of the luminance TBC 18Y is used, but in all other modes, the read address of the luminance TBC 11Y is used). .

Assuming both input and output fields are even, a vertical offset number is generated, after which the vertical offset number is temporarily lost during line conversion from 625/50 to 525/60, or from 525/60 to 625/50. When the line is temporarily repeated during conversion, it indicates the position between two input lines to which the output line should be interpolated so that a non-distorted image is generated.

When the line is repeated by the luminance TBC 11Y (18Y), a vertical freezing signal is generated.

If the input fields are not even, the interpolators 1Y and 1C must use the input field polarity and output field polarity for accurate interpolation.

The contents of the EPROM are generated in the same manner as described above in relation to the twelfth degree for the time offset signal, using line positions known in both 525 and 625 images.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited to the embodiments, and various changes by those skilled in the art without departing from the spirit and scope of the present invention as defined by the claims. And modifications may be made.

Claims (4)

A television system converting a first television system into a second television system, wherein the second television system and the first television system have different lines per frame and different fields per second. A medium having a television input signal of a television system, having a field per second equal to the first and second television systems, and a line per frame which is an intermediate value of lines per frame of the first and second television systems. Time axis correction means for generating a television signal in a format, wherein the median of the number of lines per frame is selected such that all lines of the television signal in the intermediate format have the same total number of pixels; Analysis means for analyzing the operation between successive fields of the intermediate format television signal; Alignment means for aligning the continuous fields according to the analyzed operation to effectively represent a still picture; And means for effectively converting by using the still image to obtain the television output signal of the second television system. A television field converter of 625 lines 50 fields per second to 525 lines 60 fields per second, which receives an input 625 lines 50 fields digital television signal per second and has 60 fields per second and lines per frame that is halfway between 625 and 525. A four-field time base corrector with outputting all lines having the same number of pixels in total; An operation analyzer attached to the output of the time base corrector, for analyzing the operation of the television input signal and providing corresponding image motion data; A shift register attached to an output of the time base corrector; An interpolator for generating a sample of a 525-line 60 field digital television signal per second based on the image motion data output by the motion analyzer and a sample output from the shift register; And a two-field time base corrector combining the output samples to form the television output signal. A 525 lines 60 fields per second to 625 lines 50 fields per second television format converter, receiving an input 525 lines 60 fields per second digital television signal, an intermediate format having 60 fields per second and lines per frame that is halfway between 525 and 625 A two-field time base corrector for outputting a television signal of which all lines have the same number of pixels in total; An operation analyzer attached to the output of the time base corrector, for analyzing the operation of the television input signal and providing corresponding image motion data; A shift register attached to an output of the time base corrector; An interpolator for generating a sample of a 625-line 50-field digital television signal per second based on the image motion data output by the motion analyzer and a sample output from the shift register; And a four-field time base corrector combining the output samples to form the television output signal. A slow motion processor, comprising: an input circuit for receiving a digital television input signal; A motion analyzer for analyzing the operation of the digital television input signal and providing corresponding image motion data, and a shift register for holding successive other fields of the television input signal; An interpolator for generating a sample of a predetermined slow motion digital television output signal in accordance with a sample obtained from the shift register, image motion data output by the motion analyzer, and a degree of slow motion; And a two-field time base corrector for combining the generated samples to form a slow motion television output signal.

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