JPS61138376A - System for selecting, synthesizing and controlling circuit - Google Patents

Abstract

PURPOSE:To select an optimum circuit according to a design guideline by setting a priority coefficient in accordance with the design guideline and selecting a development candidate circuit having a maximum valuation. CONSTITUTION:With a functional chart given, the search or selection of a macro on the functional chart is executed. If the selection of the macro is not finished, the development candidate circuit of the macro is obtained. This can be done by reading the development candidate circuit according to a development rule from a file device 4. Then the priority coefficient of an indicated checking item is multiplied at every development candidate circuit to obtain the valuation. The valuation corresponding to the development circuit can be obtained in the prescribed area of a main memory 3 by multiplying coefficients with the aid of a processor while a table 6 is referred. The highest valuation is found by a comparison function of the processor 1, and the development candidate circuit corresponding to the valuation is selected. This procedure is repeated until the search or selection of the macro is terminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a circuit selection and synthesis control method for synthesizing a circuit based on a functional diagram using a circuit selected from a plurality of development candidate circuits corresponding to the functional diagram. It is related to.

[Conventional technology]

In the design of large-scale integrated circuits (LSI) and circuit designs using circuit elements including them, CAD (compute
The advanced design method is often adopted. In conventional circuit selection and synthesis control methods using computers, multiple expansion candidate circuits are stored in advance in a file memory, etc. for a functional diagram that defines the functions of the circuit scale of each unit. , when a functional diagram is given, a deployment candidate circuit corresponding to the functional diagram is determined according to a predetermined deployment rule, and the deployment candidate circuit selected from among them according to the priority order is used. In that case,
For example, set the priority of multiple deployment candidate circuits high for circuits with a small number of basic cells, lower them for circuits with a large number of basic cells, and check items such as the number of inputs in order of priority. A method is often adopted in which a check is performed and a circuit that satisfies all the check items is selected first.

[Problem that the invention seeks to solve]

The circuit selected from multiple deployment candidate circuits corresponding to the functional diagram will be greatly influenced by the priority order, and if the priority order is determined by the basic number of cells, the number of circuit elements will be minimized. However, when it is necessary to configure a circuit with emphasis on reliability, driving ability, etc., there is a drawback that it cannot be handled. Furthermore, since the check items are fixed, it is not possible to perform checks corresponding to the types of elements on the functional diagram (hereinafter referred to as macro).

The present invention improves the above-mentioned conventional drawbacks, makes it possible to comprehensively evaluate all of a plurality of macro-compatible expansion candidate circuits, select the optimal expansion candidate circuit, and
The purpose is to enable circuit synthesis according to design principles.

[Means for solving problems]

The circuit selection synthesis control method of the present invention provides a table having check items and priority coefficients that can be set for the check items for multiple deployment candidate circuits corresponding to macros, and provides a functional diagram. Sometimes, an evaluation value is obtained by multiplying each expansion candidate circuit for the macro in this functional diagram by the priority coefficient for the check item, and the expansion candidate circuit with the maximum evaluation value is selected.

[Effect]

By setting the priority coefficients according to the design policy, the evaluation value of each deployment candidate circuit will be higher as the circuit is most suitable for the design policy.Therefore, it is possible to select the deployment candidate circuit with the maximum evaluation value. This makes it possible to select the optimal circuit for the design policy.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a processor (CPU), 2 is a program memory (PRM), and 2 is a block diagram of an embodiment of the present invention.
), 3 is the main memory (MM), and 4 is a file device (F) such as a magnetic disk device that stores expansion candidate circuits, etc.
5 is a display device (DSP), 6 is a table (TB) having check items CH and priority coefficients P, and 7 is a cell library (CEL).

As shown in Figure 2, the cell library 7 stores cell names, functions, basic cell numbers, drive capacities, etc.
For example, the function of cell name A is OR circuit OR2;
The next 2 indicates the number of inputs, and the basic number of cells is 2. Also, the function of cell name C is inverter INV, the basic number of cells is 1, and the drive capacity is 18, and the function of cell name E is inverter INV, the basic number of cells is 1, and the drive capacity is 2 of cell name C. That's 36 times as many. Also, the function of cell name G is an AND circuit AND2, the number of inputs is 2, and the number of basic cells is 2.
It is. In this way, functions including the number of inputs, the basic number of cells, drive capacity, etc. are stored in correspondence with the cell name.

Further, the file device 4 stores expansion candidate circuits corresponding to macros for each unit function, etc. For example, the expansion candidate circuit of the four-person Chaor circuit shown in (A) of FIG. al), (a2), (a3), . . . and each cell name is given. Furthermore, depending on the expansion candidate circuit, one or more macros may be included.

Further, in the table 6, check items and priority coefficients are set for each expansion candidate circuit, as shown in FIG. For example, the priority coefficient P1 for the check item of whether or not a deployment candidate circuit can be used is set to 1 if it is usable, and 0 if it is not usable. In addition, the priority coefficient P2 for the check item for the number of inputs is set depending on the number of inputs in the functional diagram, and is set to 1 when the number of inputs is the same, and when there is room for the number of inputs in the expansion candidate circuit. , is set to 1 or less.

The priority coefficient P3 for the check item of the number of basic cells is set to a value closer to 1 as the number of basic cells is smaller, and the priority coefficient P4 for the check item of the number of wires is set to a value closer to 1 as the number of wires between cells is smaller. Set a similar value. The priority coefficient P5 for reliability check items is set to a value closer to 1 as the reliability is higher. These priority coefficients P can also be changed during circuit design.

When a functional diagram is given, the macros in the functional diagram are sequentially identified by the processor l, or the display device 5
The designer can specify the functional diagram displayed on the screen using the keyboard, mouse, etc. Thereby, according to the expansion rule program stored in the program memory 2, expansion candidate circuits corresponding to the macro are sequentially read out from the file device 4 and displayed on the display device 5 in, for example, a multi-window format.

An evaluation value is obtained for each expansion candidate circuit corresponding to this macro, and the evaluation value F is determined by the priority coefficients P1, P2, . P3.・
. . is obtained by multiplying by the processor 1. Therefore, the evaluation value for an unusable expansion candidate circuit is the priority coefficient P of the check item for its usability.
Since 1 becomes 0, it becomes 0. Then, when evaluation values are obtained for each expansion candidate circuit, for example, as shown in FIG. 5, expansion candidate circuits al, a2, . a3. ...an
Evaluation values Fl, F2. F3. ... Since Fn is obtained, the evaluation value comparison process by the processor 1 yields,
Find the maximum evaluation value and select the expansion candidate circuit corresponding to that evaluation value. This circuit will be used to perform the synthesis process.

For example, for the macro in (A) in Figure 3, the expansion candidate circuit (al) cannot be used, and the expansion candidate circuit (a2) cannot be used.
, (a3) can be used, and the priority coefficient P2 of the check item for the number of inputs is set to 1, for example, since both numbers are the same as the number of macro inputs, and the priority coefficient P2 for the check item of the basic cell number is set to 1. Since the total number of basic cells can be determined by referring to the cell library 7, P3 is an expansion candidate circuit C22 with the same number of basic cells.
).

For (a3), set the same value, for example, 0.7.

Also, the priority coefficient P4 for the check item of the number of wires is
It is set according to the number of wires between cells, and the expansion candidate circuit (a2) has two wires connecting two OR circuits and one OR circuit. a3
), the number of wires connecting four inverters and one NAND circuit is 4, so the priority coefficient P4 of the expansion candidate circuit (a2) is, for example, 0.9, and the expansion candidate circuit (a3) The priority coefficient P4 is, for example, 0.
6. Also, the priority coefficient P5 of the reliability check item is set to a value close to 1 for deployment candidate circuits with high reliability; for example, 0.8 for deployment candidate circuit (a2), 0.8 for deployment candidate circuit (a2), 0.9 can be set for a3).

Assuming that the priority coefficients for the check items are set as described above, the evaluation value of the expansion candidate circuit (al) is O, and the evaluation value of the expansion candidate circuit (a2) is 1 x 1
x O, 7x O, 9x 0.8 = 0.504, and the evaluation value of the expansion candidate circuit (a3) is 1x 1
x 0.7 x 0.6 x O,9 = 0.378. Therefore, since the evaluation value of the expansion candidate circuit (a2) is the maximum, this expansion candidate circuit (a2) is selected to realize the macro (A).

For check items that do not need to be checked, evaluation values are determined without using the corresponding priority coefficients.

For example, if you do not need to check the number of wires,
In the above example, since the evaluation value of the expansion candidate circuit (a3) is the maximum, this expansion candidate circuit (a3) is selected.

In addition, when calculating the evaluation value for the expansion candidate circuit for the same macro, the priority coefficient of the predetermined check item is further multiplied by a function according to the importance of the functional diagram in the circuit position r of the entire device. You can also calculate the evaluation value after doing so. For example, in a functional diagram consisting of
If it is important that the number of wires is small, the evaluation value can be obtained after multiplying the priority coefficient P4 by a function. Further, if the expansion candidate circuit that constitutes the expansion candidate circuit with the maximum evaluation value further includes a macro, the same selection process as described above is performed for that macro. If it is difficult to realize the expansion candidate circuit with the highest evaluation value, the expansion candidate circuit with the second highest evaluation value is selected.

FIG. 6 shows an example of a flowchart of an embodiment of the present invention. When a functional diagram is given, a search or selection of a macro in the functional diagram is performed, and if the macro selection is not completed, Find expansion candidate circuits for the macro. This can be obtained by reading out the expansion candidate circuit from the file device 4 according to the expansion rule, as described above. Next, for each expansion candidate circuit, an evaluation value F is obtained by multiplying the priority coefficient P of the specified check item. As described above, by referring to table 6 and performing multiplication processing by processor 1, evaluation values corresponding to the expansion candidate circuit as shown in FIG. 5 are obtained in a predetermined area of main memory 1. It is something. Then, the largest value for each evaluation value is found by the comparison function of the processor 1, and the expansion candidate circuit corresponding to the evaluation value is selected. This process is repeated until the macro search or selection is completed.

In this way, after a deployment candidate circuit is selected, redundant gate circuit deletion processing, gate circuit compression processing, or A drive capability determination process is performed.

〔Effect of the invention〕

As explained above, the present invention provides a table 6 in the main memory 3 or other storage means having check items corresponding to expansion candidate circuits and a priority coefficient P that can be set for the check items, and For each deployment candidate circuit, the evaluation value F is obtained by multiplying the priority coefficient P for the check item, and the deployment candidate circuit with the largest evaluation value F is selected. Since the priority coefficient P for the priority item can be set in zS, which specifies the priority item, the evaluation value F of each development candidate circuit indicates the overall value according to the design policy. , there is an advantage that the optimal circuit can be selected by selecting the expansion candidate circuit with the largest evaluation value. Therefore, selection conditions in circuit selection and synthesis can be dealt with flexibly.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a cell library of the embodiment of the present invention, FIG. 3 is a candidate circuit diagram for expansion to a functional diagram of the embodiment of the present invention, FIG. 4 is an explanatory diagram of check items and priority coefficients, FIG. 5 is an explanatory diagram of expansion candidate circuits and evaluation values, and FIG. 6 is an example of a flowchart of an embodiment of the present invention. 1 is the processor (CPU), 2 is the program memory
(PRM), 3 is main memory (MM), 4 is file device (FTL), 5 is display device (DSP
), 6 is the table (TB), and 7 is the cell library (
CEI, ).

Claims (1)

[Claims] In a circuit selection synthesis control method that obtains a plurality of expansion candidate circuits from a functional diagram, and selects and synthesizes a realizable circuit from the expansion candidate circuits, there are check items corresponding to the expansion candidate circuits, and check items for the check items. A table with priority coefficients that can be set is provided, and for each development candidate circuit,
A circuit selection and synthesis control method characterized in that an evaluation value is obtained by multiplying the check items by a priority coefficient, and a development candidate circuit with the maximum evaluation value is selected and the circuits are synthesized.