JPS61137429A - Testing circuit of ad converter - Google Patents

Abstract

PURPOSE:To check the accuracy of an AD converter through digital signal processing by providing a digital-analog (DA) converter which outputs the input voltage of an AD converter to be tested, a counter circuit which outputs the input value of the DA converter, and the 1st and the 2nd arithmetic circuits which calculate an error. CONSTITUTION:The output value of the counter circuit 1 is latched by latch circuits 4 and 5 successively every time the output value of the AD converter 8 increases by one LSB, and a subtracting circuit 6 calculates the difference between output values of the latch circuits 4 and 5 to find the quantity of variation in the output value of the counter circuit 1 corresponding to one LSB variation in the output value of the AD converter 8. The output value of the subtracting circuit 6 is compared with that of a comparator A which is set previously by a comparing circuit 7 to compare the quantity of variation in input voltage value with the one LSB variation in the output value at each input voltage point of the AD converter 8, thereby checking a differential nonlinear error.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an AD converter test circuit for checking the accuracy of an analog-to-digital converter (hereinafter abbreviated as AD converter).

In general, nonlinearity error and differential nonlinearity error are often used to express the accuracy of conventional AD converters. Figure 2 shows a diagram showing the output digital signal with respect to the input voltage of the AD converter. Nonlinearity error refers to the deviation between the measured value and the straight line connecting all 0s to all 1s of the output digital signal. The nonlinearity error represents the deviation between the theoretical value and the measured value with respect to the amount of change in the minimum bit (1LSB) at each input voltage point.

Therefore, the method to check this nonlinearity error and differential nonlinearity error is to sequentially change the input voltage of the AD converter and measure this human voltage value and the output value of the AD converter. There are possible ways to do this, but I have not been able to find any literature that provides specific examples.

Problems to be Solved by the Invention The method of measuring the input voltage of the AD converter deals with analog values, so it is difficult to process them quickly. Yoshi also requires high precision and is expensive.

In view of this, an object of the present invention is to provide an AD converter test circuit that has a simple circuit configuration and is capable of quickly checking the accuracy of an AD converter using digital signal processing.

Means for Solving the Problems In order to solve the above problems, the present invention provides a digital-to-analog converter (hereinafter referred to as D) that outputs the input voltage of the AD converter.
This is an AD converter test circuit that includes an A converter), a counter circuit that outputs the input value of this DA converter, and first and second arithmetic circuits that calculate errors.

According to the above-described configuration, the present invention can replace the input voltage of the AD converter with a digital signal that is the output value of the counter circuit, and check the accuracy of the AD converter using the digital signal theory. becomes possible.

Embodiment FIG. 1 is a block diagram showing an embodiment of the AD converter test circuit of the present invention. In FIG. 1, 1 is a counter circuit that counts the output signal 2 and outputs the counted number. 3 is a DA converter which outputs a voltage value corresponding to the output value of the counter circuit 1;

4.5 is a launch circuit which latches the output value of the counter circuit 1. 6 is a subtraction circuit that calculates the difference between the output values of the latch circuits 4.5. A comparison circuit 7 compares the output value of the subtraction circuit 6 with a preset comparison value A. 8 is AD for test
The converter inputs the output voltage value of the DA converter 3 and outputs a digital signal value corresponding to this value. The latch circuit launches the output value of the AD converter 8. A comparison circuit 10 compares the output values of the AD converter 8 and the latch circuit 9.

11 is a subtraction circuit that calculates the difference between the output values of the launch circuit 4 and the AD converter 8. A comparison circuit 12 compares the output value of the subtraction circuit 11 with a comparison value B set in advance.

The operation of the AD converter test circuit of this embodiment configured as described above will be described below. The DA converter 3 used is one with higher accuracy than the AD converter 8 under test. That is, the number of input bits of the DA converter 3 is greater than the number of output bits of the AD converter 8. The counter circuit 1 has the same number of bits as the input bit number of the DA converter 3, and is sequentially counted up from all 0 to all 1 by the clock signal 2. As a result, the output voltage value of the DA converter 3 changes sequentially from the lowest value to the highest value. The AD converter 8 under test receives the output voltage of the DA converter 3 and outputs a digital signal value corresponding to the voltage value. This output value is latched by the launch circuit 9, and compared with the next output value of the AD converter 8 by the comparison circuit 1o. If the output value of the AD converter 8 is larger, a signal is output from the comparison circuit 1o. That is, the point at which the output value of the AD converter 8 increases by 1 LSB is detected. By using the output signal of the comparator circuit 10 as a signal for the latch circuits 4 and 5, the output value of the counter circuit 1 is sequentially sent to the latch circuits 4 and 6 every time the output value of the AD converter 8 increases by 1LSB. It gets latched. By calculating the difference between the output values of the latch circuits 4 and 5, the subtraction circuit 6 can determine the amount of change in the output value of the counter circuit 1 that corresponds to a change of 1 LSB in the output value of the AD converter 8. In other words, the amount of change in the input voltage value required for the output value of the AD converter 8 to change by 1 LSB is replaced by the amount of change in the output value of the counter circuit 1. Now, if the number of bits of the counter circuit 1 is 1 pit more than the number of output bits of the AD converter 8, then under ideal conditions with no error, the output value of the AD converter 8 is 1.
When the LSB changes, the output value of the counter circuit 1 changes by 2 bits. Similarly, if the number of bits of counter circuit 1 is 2 bits more than the number of output bits of AD converter 8, then AD
If the output value of converter 8 changes by 1LSB, counter circuit 1
The output value changes by 4 pits.

In other words, as the number of bits of the counter circuit 1 is larger than the number of output bits of the AD converter 8, the number of bits that the output value of the counter circuit 1 changes in response to a change of 1 LSB in the output value of the AD converter 8 increases. In other words, it has good accuracy (A
This means that the amount of change in the input voltage value corresponding to a 1 LSB change in the output value of the D converter 8 can be replaced with the amount of change in the output value of the counter circuit 1.

By comparing the output value of the subtraction circuit 6 and a preset comparison value A in the comparison circuit 7, the input voltage value corresponding to a 1 LSB change in the output value at each input voltage point of the AD converter 8 is determined. The amount of change will be compared, and differential nonlinearity errors can be checked. That is, by setting the value of comparison value A to the amount of change in the output value of the counter circuit 1 corresponding to 1 LSB of the output value of the AD converter 8, it is possible to determine whether the differential nonlinearity error is within 1 LSB. Can be checked. Also, AD the value of comparison value A
By setting the amount of change in the output value of the counter circuit 1 corresponding to 1/2 LSB of the output value of the converter 8,
It is possible to check whether the differential nonlinearity error is within 1/2 LSB.

On the other hand, the subtraction circuit 11 calculates the difference between the output value of the AD converter 8 and the output value of the latch circuit 4.

The output value of the counter circuit 1 is latched in the latch circuit 4, which corresponds to the input voltage value for the output value of the AD converter 8, and represents the measured value in the graph of FIG. Because of the difference in the output of the circuit 8, the subtraction circuit 11 needs to perform calculations by aligning the upper bits first.

Then, the output value of the subtraction circuit 11 and the preset comparison value B are compared in the comparison circuit 12, and the nonlinearity error is checked in the same manner as in the case of the differential nonlinearity error. Can be done.

As described in detail, according to the present invention, nonlinearity errors and differential nonlinearity errors can be quickly checked with a simple circuit configuration, and error accuracy can also be easily set. Furthermore, since processing is performed using digital signals, automatic testing can be easily performed, and its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an AD converter test circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an output digital signal with respect to an input voltage of the AD converter. 1... Counter circuit, 3... DA converter, 4゜5.9-... Latch circuit, 6, 11...
...subtraction circuit, 7.10.12...comparison circuit,
8...AD converter. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A DA converter that outputs the input voltage of the AD converter, a counter circuit that outputs the input value of the DA converter, a detection circuit that detects a change of 1 LSB in the output value of the AD converter, and a latch circuit that latches the output value of the counter circuit using the output of the detection circuit; a first arithmetic circuit that calculates a differential nonlinearity error from the output value of the latch circuit; An AD converter test circuit comprising: a second arithmetic circuit that calculates a nonlinearity error from an output value of the converter.