JPS61136710A - Manufacturing method of substrate for multi-layer printed circuit - Google Patents
Manufacturing method of substrate for multi-layer printed circuitInfo
- Publication number
- JPS61136710A JPS61136710A JP25546784A JP25546784A JPS61136710A JP S61136710 A JPS61136710 A JP S61136710A JP 25546784 A JP25546784 A JP 25546784A JP 25546784 A JP25546784 A JP 25546784A JP S61136710 A JPS61136710 A JP S61136710A
- Authority
- JP
- Japan
- Prior art keywords
- marks
- inner layer
- mark
- printed circuit
- position sensing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は電子機器、電電機器、伝送機器、無線機器、計
算機器等に用いられる多層印刷回路用基板の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a multilayer printed circuit board used in electronic equipment, electrical and electrical equipment, transmission equipment, wireless equipment, computing equipment, and the like.
従来の多層印刷回路用基板の位置検出用孔位置表示は、
熟練作業者が孔位置表示埋設推定場所を悪により徐々に
座ぐり加工して表示部を露出させていたものであるが、
埋設推定場所の位置間違い、座ぐり不足による表示部の
不鮮明、座ぐり過剰による表示部の消滅、座ぐり作業の
不能率、熟練作業者の不足等が問題になり、更に二次成
型後の工程を自動化できない欠点があった。The conventional hole position display for position detection on multilayer printed circuit boards is
Skilled workers used to gradually counterbore the estimated burial location of the hole position display to expose the display section.
Problems such as the incorrect location of the estimated burial site, blurring of the display due to insufficient counterboring, disappearance of the display due to excessive counterboring, inability to perform counterboring work, and lack of skilled workers have become a problem, as well as problems with the post-secondary molding process. The disadvantage was that it could not be automated.
本発明の目的とするところは多層印刷回路板加工時の基
準となる位置検出用マークを正確に孔あけして表示せし
めることにある。An object of the present invention is to accurately drill and display position detection marks that serve as references when processing a multilayer printed circuit board.
本発明は内層材端部に複数個の位置検出用マークを設け
てから、内層材両側に1リゾレグ及び外層材をこの順に
重ね合せ加熱加圧後、該マーク部を渦電流検出型センサ
ーで検知後、座ぐり加工して露出させ、該マークを基準
として加工するため、マーク位置を±200ミクロン程
度と正確にすることができるので二次成形後の座ぐり、
孔あけ、外形仕上げ工程等を自動化且つ連子して行なう
ことができるようになったものである。以下本発明の一
実施例を図示実施例に基づいて説明する。In the present invention, a plurality of position detection marks are provided at the end of the inner layer material, and then one Resoreg and the outer layer material are stacked on both sides of the inner layer material in this order, heated and pressed, and then the mark portions are detected by an eddy current detection sensor. After that, the counterbore is exposed and processed using the mark as a reference, so the mark position can be accurate to about ±200 microns, so the counterbore after secondary molding,
It has become possible to automate and coordinate processes such as drilling holes and finishing the external shape. An embodiment of the present invention will be described below based on an illustrated embodiment.
図面に示すように片面銅張積層板や両面銅張積層板の表
面に回路を形成した内層材1.1′の端部、好ましくは
隅部に複数個の位置検出用マーク2.2.2.2全設け
てから、内層材両側にフェノールIHIW、エポキシ樹
脂、不飽和ポリエスデA/樹脂、メラミン樹脂、ポリイ
ミド、ポリブタジェン、ポリアミド、ポリアミドイミド
、ポリスルフォン、ポリブチレンテレフタレート、ポリ
エーテルエーテルケトン、弗化樹脂等の単独、変性物、
混合物等からなる合成樹脂フェスをガラス、アスベスト
等の無機繊維やポリエスデ〃、ポリアミド、ポリビニル
アμコール、アクリル等の有機合成繊維や木綿等の天然
繊維からなる織布、不織布、マット或は紙等の基材に含
浸、乾燥させたプリプレグ3及び銅箔、アルミニウム箔
、真鍮箔、ニッケ/L’箔等の金属箔や片面金属箔張積
層板等の外層材4をこの順に重ね合せて加熱加圧後、該
マーク部2t−渦電流検出型センサーで検知後、座ぐり
加工して露出させ、該マーク2を基準としてスルホール
孔あけ加工や外形仕上げ加工等の加工をするものである
。位置検出用マークは金属であるならばよく、内層材の
回路形成時に金属箔張積層板の一部を用いてマークとし
てもよく、又金属箔等を接着してマークとしてもよく特
に限定するものではないが、好ましくは金属箔であるこ
とが望ましいことである。As shown in the drawings, a plurality of position detection marks 2.2.2 are provided at the end, preferably at the corner, of an inner layer material 1.1' in which a circuit is formed on the surface of a single-sided copper-clad laminate or a double-sided copper-clad laminate. .2 After installing all the inner layer materials, apply phenol IHIW, epoxy resin, unsaturated polyester A/resin, melamine resin, polyimide, polybutadiene, polyamide, polyamideimide, polysulfone, polybutylene terephthalate, polyether ether ketone, fluoride to both sides of the inner layer material. Single resin, modified product,
Synthetic resin faces made of mixtures, etc. can be replaced with woven fabrics, non-woven fabrics, mats, paper, etc. made of inorganic fibers such as glass and asbestos, organic synthetic fibers such as polyester, polyamide, polyvinyl alcohol, acrylic, and natural fibers such as cotton. The prepreg 3 impregnated and dried on the base material and the outer layer material 4 such as metal foil such as copper foil, aluminum foil, brass foil, nickel/L' foil, or single-sided metal foil-clad laminate are laminated in this order and heated. After pressing, the mark portion 2t is detected by an eddy current detection sensor, then counterbored to expose the mark portion 2t, and processing such as through-hole drilling and external finishing is performed using the mark 2 as a reference. The mark for position detection may be made of metal as long as it is made of metal, and it may be made by using a part of the metal foil-clad laminate when forming the circuit of the inner layer material, or it may be made by gluing metal foil, etc. There are no particular limitations. However, it is preferable to use metal foil.
上記のように本発明の方法によれば、正確な位置検出用
マーク位置を知ることができるので位置検出用孔位置表
示埋設推定場所の位置rlll】違いが解消し、又座ぐ
り不足や座ぐり過剰が解消し更に座ぐり作業能率の向上
、熟練作業者が不要になり更に二次成形後の工程を自動
化できるようになったものである。As described above, according to the method of the present invention, it is possible to know the exact position of the mark for position detection, so it is possible to eliminate the difference in the position of the hole position display for position detection and the estimated burial place. This eliminates the problem of excessive production, improves the efficiency of counterboring work, eliminates the need for skilled workers, and automates the process after secondary forming.
図面は本発明の方法の一実施例により多層印刷回路用基
板材料を積層した場合の簡略断面図である。
1は内層材、2は位置検出用マーク、3はプリプレグ、
4は外層材である。The drawing is a simplified cross-sectional view of a multilayer printed circuit board material laminated according to an embodiment of the method of the present invention. 1 is the inner layer material, 2 is the position detection mark, 3 is the prepreg,
4 is an outer layer material.
Claims (2)
から、内層材両側にプリプレグ及び外層材をこの順に重
ね合せ加熱加圧後、該マーク部を渦電流検出型センサー
で検知後、座ぐり加工して露出させ、該マークを基準と
して加工することを特徴とする多層印刷回路用基板の製
造方法。(1) After providing multiple position detection marks on the edge of the inner layer material, heat and press the prepreg and outer layer materials on both sides of the inner layer material in this order, and then detect the marks with an eddy current detection sensor. . A method for manufacturing a multilayer printed circuit board, comprising: performing a counterbore process to expose the mark, and processing the board using the mark as a reference.
る特許請求の範囲第1項記載の多層印刷回路用基板の製
造方法。(2) The method for manufacturing a multilayer printed circuit board according to claim 1, wherein the position detection mark is a metal foil.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25546784A JPS61136710A (en) | 1984-12-03 | 1984-12-03 | Manufacturing method of substrate for multi-layer printed circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25546784A JPS61136710A (en) | 1984-12-03 | 1984-12-03 | Manufacturing method of substrate for multi-layer printed circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61136710A true JPS61136710A (en) | 1986-06-24 |
Family
ID=17279168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25546784A Pending JPS61136710A (en) | 1984-12-03 | 1984-12-03 | Manufacturing method of substrate for multi-layer printed circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61136710A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03126235A (en) * | 1989-10-12 | 1991-05-29 | Nippon Micron Kk | Manufacture of pin grid array having structure of multistage bonding terminal, precutting apparatus for inner layer terminal and multilayered board for pin grid array |
JPH05121879A (en) * | 1991-10-30 | 1993-05-18 | Nec Corp | Manufacture of multilayer printed wiring board |
WO2012034152A1 (en) * | 2010-09-17 | 2012-03-22 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a circuit board consisting of a plurality of circuit board areas and circuit board |
-
1984
- 1984-12-03 JP JP25546784A patent/JPS61136710A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03126235A (en) * | 1989-10-12 | 1991-05-29 | Nippon Micron Kk | Manufacture of pin grid array having structure of multistage bonding terminal, precutting apparatus for inner layer terminal and multilayered board for pin grid array |
JPH05121879A (en) * | 1991-10-30 | 1993-05-18 | Nec Corp | Manufacture of multilayer printed wiring board |
WO2012034152A1 (en) * | 2010-09-17 | 2012-03-22 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a circuit board consisting of a plurality of circuit board areas and circuit board |
US9226390B2 (en) | 2010-09-17 | 2015-12-29 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a circuit board consisting of a plurality of circuit board areas and circuit board |
US10321558B2 (en) | 2010-09-17 | 2019-06-11 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Printed circuit board |
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