JPS61136238A - Semiconductor device - Google Patents

Abstract

PURPOSE:To produce a semiconductor with even pressure fitting load, excellent electric and mechanical characteristics by a method wherein a gate electrode sheet is buried in an intermediate slidable sheet to be integrated therewith through an insulator while a gate fetch part is provided on the central part of intermediate slidable sheet. CONSTITUTION:When a semiconductor substrate 1 is pressure fitted with an integrated intermediate slidable sheet 100 comprising a gate electrode sheet 102 and a cathode electrode sheet 101 integrated with each other through an insulator 105, said substrate 1 and slidable sheet 100 are equally brought into contact with a gate electrode 6 on an N emitter 5 and a gate fetch part 7-1 of protruding part 40 of P base. The plane whereon a gate sheet 102' of integrated intermediate sheet 100 and extruded cathode electrode sheet 101 are brought into contact with the semiconductor 1 and an upper electrode block 60 is finished on the same plane at specified precision while a part 103 coming into contact with a control electrode lead wire is free-rotatably provided on the central part of intermediate slidable sheet 100 one step lower than the surface making it feasible to align each member during pack-aging process.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device in which a pair of main electrodes can be turned on and off by a control signal applied between a control', - pole and one main electrode. In particular, the present invention relates to an improvement in the structure of an electrode plate that presses into contact with a main electrode.

[Background of the invention]

A transistor (hereinafter abbreviated as TRY) is used as a semiconductor device to turn on and off the load current according to a control signal. Gateter/or thyristors (hereinafter abbreviated as GTO), field effect thyristors (hereinafter abbreviated as POT), and the like are known. These TR8-? In GTO and FCT "t", the emitter layer of the semiconductor substrate is divided into fine strips, and each emitter layer is provided with an emitter electrode film and a cathode electrode film, and the adjacent base layer is provided with a base electrode film and a gate electrode film. The electrode film is arranged so as to surround each Niotsuta layer to speed up the extraction of carriers from the base layer at turn-off, thereby enabling high-speed operation.

When 'I'R'3.0TO, F'C'l'' becomes large capacitance, the emitter electrode Il!-e cando electrode film is
At the same time as pressing the tkt electrode through an intermediate sliding plate and pressing the base lead and gate lead against the base electrode film and gate electrode film, the semiconductor substrate may be destroyed due to the difference in thermal expansion coefficient between the members. This prevents characteristic fatigue and simplifies the electrode structure. The following known examples have been disclosed as structures of semiconductor devices accompanying such increased capacity.

As semiconductor substrates become larger in diameter, Utility Model Application No. 58-81939 and Utility Model Application No. 58-158452 have been developed to make the pull-out resistance of the base or gate electrode uniform within the plane and improve the uniformity of operation. Disclosed. These have an advantageous structure in terms of improving characteristics on the semiconductor substrate side, but there is a problem in the structure of the intermediate sliding plate that contacts the cathode electrode film and the gate electrode film when pressing these together. If the features of the semiconductor substrate cannot be fully exploited and the intermediate sliding plate in contact with the cathode electrode is divided into two or more pieces, stress and strain will occur due to pressurization in their peripheral areas, causing local damage to the cathode electrode film. pressure is applied to
In this area, there were problems such as poor contact between the cathode and gate due to the electrode collapse, and sticking to the semiconductor substrate due to electrode creep at the pressure contact portion, making it impossible to operate.

[Purpose of the invention]

The purpose of the present invention is to solve the problems of the conventional structure, and to provide a semiconductor device which has a uniform pressure load due to an intermediate sliding plate, has good electrical and mechanical properties, and is easy to assemble. There is a particular thing.

[Summary of the invention]

The present invention is characterized in that a gate electrode plate (i.e. +ff1J control electrode plate) is provided in contact with the gate electrode at fc to bring the gate current extraction portion and each operating region electrically close, and The plate is connected to the intermediate sliding plate of the main electrode plate through an insulator, and the surface in contact with the main surface of the semiconductor holder has a gate 11cfII11 plate embedded integrally.
This integrated electronic board and the four semiconductors are placed opposite each other and brought into contact with each other.Furthermore, the external gate drawer is provided at the center of the intermediate sliding plate to create a center gate structure that can be easily assembled and rotated. Ruru.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail based on a specific example 72, taking the present invention t-G'l'0' as an example.

FIG. 3 is a plan view of a conventional GTO base, and FIG. 1 is a sectional view of a package in which a GTO base according to an embodiment of the present invention is enclosed.

In the figure, a semiconductor substrate 1 has a cathode electrode 6.1 which is one main electrode that is ohmically connected to the p emitter 2, the n base 3, the p base 4, the n emitter 5, and the emitter 5.
II on the surface on the same side as the exposed surface of 1. ft:, gate electrode 7 which is a control electrode ohmically connected to p base 4
, an anode electrode plate 8 which is the other main electrode and which is ohmically connected to the gate electrode 7 and the external electrode plate, and is ohmically connected to the nine-shaped gate electrode 7-1 and the p-shaped ivy 2.

Generally, the arrangement of n emitters is as shown in FIG.
is surrounded by the gate electrode 7. In addition, the gate electrode surrounding the cathode electrode is connected to the external electrode extraction portion 7-1 in a link shape approximately at the center of the GTO element.
It is established as. The pnpn four-layer region including the n-emitter 5 is the operating region, and the pnp three-layer region adjacent to the operating region is the control region.

The reason for the above arrangement is to efficiently turn off a large load current. That is, by surrounding the elongated emitter with the gate electrode t, the distance between the farthest region of the emitter and the gate is made uniform, and the turn-off signal from the gate electrode acts uniformly over the entire operating region. By arranging a large number of such n emitters, the overall operating area is enlarged and the current capacity of the element is increased.

Furthermore, the n-emitters are arranged radially from the center of the base, making it easy to incorporate them into the package. The above-mentioned conventional techniques have been proposed to incorporate such a GTO element having the structure shown in FIG.

The present invention relates to a packaging method that can fully demonstrate the performance of the fI-structure GTO element in response to the increase in capacity, is easy to incorporate, and is highly reliable. However, the integrated intermediate sliding plate 10
It is at 0.

The n emitter 5 of the semiconductor substrate 1 has a rectangular shape of about 0.2 m in width and about 5 m in length, and protrudes by about 30 μm from the surface of the adjacent p base 40, and is coated with an At vapor deposited film with a thickness of about 10 μm on its surface. The cathode electrode 6 is in ohmic contact. More than 150 N emitters 5 having such a shape and structure are arranged in a double radial pattern on the surface of the disc-shaped base 1.

As described above, the area surrounding the n emitter 50 is approximately 10 mm thick.
The gate electrode 7 made of a vapor-deposited film has a depth of μm on the substrate surface.
It is in ohmic contact with the electric part of the base 4. A part of the p-base is formed to protrude at the same height as the n-emitter, and the electrode 7 is also continuous with the surface portion 7-1 of the protruding portion 40 of the p-base 4. , is pressed into contact with the gate electrode plate 102 at this portion.

This protruding portion 40 of the p-paste layer is provided in the form of an intermediate portion K IJ of the radially double-arranged cathode emitters 5, and its surface height is substantially the same as that of the radially double-arranged cathode emitters 5. Therefore, when the semiconductor substrate 1 and the integrated intermediate r# moving plate 100 placed on the gate electrode plate 102 and the cathode electrode plate 101 are pressure-welded, both are connected to the n emitter 5. Upper gate electrode 6 and gate extraction portion 7 of the protruding portion 40 of the p base
-1 are in equal contact with each other.

Next, the cathode electrode plate 101 is made of tungsten steel with a thickness of 3 cm.
(W) disk t) Inside this W disk 101 is a gate electrode plate 1 made of a molybdenum material with a coefficient of thermal expansion close to W.
02 is partially exposed on one surface of the cathode electrode plate 101 which is in contact with the semiconductor substrate surface, and is embedded in the following state to form an integrated structure. Furthermore, a center gate portion 103 with which a control electrode lead wire 104 comes into contact is exposed at the center of the other surface of the buried gate electrode plate that is in contact with the upper electrode block 60 . These gate electrode plate 102 and cathode electrode plate 101 are completely electrically insulated via an insulating object 105. In this embodiment, ceramics are used as the insulator. FIG. 2 shows the parts and assembly flow of the integrated intermediate sliding plate 1000 in the embodiment of FIG. 1.

FIG. 2(a) shows the gate electrode plates 102, 102'(b)
is the cathode electrode plate 101, (C) and (C') are (a
This is an external view of the gate electrode plates 102 and 102' of ) integrated into the opening of the cathode electrode plate 101 of Φ) via an insulator 105, and (C) is the upper electrode block 60 of FIG.
(C') of the surface in contact with , shows the appearance of the other surface in contact with the main semiconductor surface of (b).

In this example, the 1st K has the following features:
At least the gate plate 102' of the integrated intermediate sliding plate 1oo
The surface where the cathode electrode plate 101 is exposed and comes into contact with the semiconductor substrate 1 and the upper electrode block 6o is finished on the same plane with a predetermined degree of sliding, which is the first feature of this embodiment.

The second integrated intermediate sliding plate 1oo has a portion 103 in contact with the control electrode lead wire provided at the center of the intermediate sliding plate lOO one step lower than the surface, which allows for free rotation and also improves the packaging. This makes it possible to align each member during the process.

If the intermediate sliding plate and the semiconductor substrate have the above structure, good contact can be obtained with a uniform load without depending on either of the cathode gates.

According to this embodiment, there are the following effects.

- Since the gate lead plate and the cathode electrode plate are integrated into a single plate using an insulating material, it is possible to prevent short-circuit accidents in the gate power node due to contact between the two.

■ Providing a gate take-out part in the center of the integrated sliding plate allows the sliding plate to rotate freely, and no load is applied to the lead gate, eliminating gate disconnection defects.

■ The integrated sliding plate has a simple center gate structure, making assembly easier and increasing productivity.

Although the present invention has been described above with reference to specific embodiments, the present invention is not limited to these examples. For example, the metal material of the canned electrode plate f1 and the gate electrode plate is W.

It is not limited to Mo, and any material may be used as long as it is a good conductor material with a similar coefficient of thermal expansion to the semiconductor substrate, such as a C, -C composite material. Also, when integrating the gate electrode plate and the cathode electrode plate, The effects of the present invention can also be obtained as long as the insulator interposed between the two is not limited to ceramics, but is a material with excellent adhesive strength and pressure resistance, such as a polyimide film or glass material.

Next, in this embodiment, the gate plate of the integrated intermediate sliding plate is in contact with the ring gate electrode portion of the semiconductor substrate at some points; Of course, even if you embed a shaped gate plate, it will still be effective.

Next, the semiconductor device is not limited to the GTO, but the present invention can be applied to any power semiconductor device having a fine pattern, such as a buck transistor f1 field effect thyristor or a reverse blocking thyristor.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing an embodiment of the present invention assembled into a package, Fig. 2 is a manufacturing flow chart of an integrated electrode plate of the invention, and Fig. 3 is a cathode of a conventional power GTO thyristor. FIG. 3 is a plan view showing an example of a pattern. l...Semiconductor base, 6...Cathode electrode, 7...
Gate electrode, 101...Cathode 11 It woodcutter plate, 10
2...Gate tight Z diagram

Claims (1)

[Claims] 1. A semiconductor substrate having two main surfaces, on one of which a plurality of operating regions and a control region surrounding the operating regions are exposed; and one main surface provided on the surface of the plurality of operating regions. A main electrode and a control electrode provided on the surface of the control area, and one main electrode plate and a control electrode plate that are pressurized to at least a portion of these electrodes are integrated via an electrical insulator. In a semiconductor device equipped with an integrated electrode plate, a part of the center of the control electrode plate embedded in the integrated electrode plate is exposed at the center of the integrated electrode plate, and the control electrode terminal portion is inserted through the exposed portion. A semiconductor device characterized in that it was taken out.