JPS6113478A - Discrimination system for digital signal level - Google Patents

Abstract

PURPOSE:To vary a threshold voltage following up abrupt variation in input digital signal level and to discriminate a signal level accurately by detecting a wrong bit in the bit array of a digital signal whose signal level is discriminated according to the regularity of the array, and then switching level discriminating means according to the detection result. CONSTITUTION:Bit error detection outputs ''1'' of detection output AND circuits ADa and ADb are ORed by an OR circuit ORC, whose output is supplied to a multivibrator MV. Then, a time constant circuit R.Ca is set properly, and when the detection output ''1'' is supplied to the multivibrator MV, the Q output of the multivibrator MV connects a level ''1'' for a period of about 10 bits; and the Q output ''1'' is supplied to the inverted input terminal of the output AND circuit ADbn of a simplified correcting circuit and the other output AND circuit ADan in parallel. Then, level discrimination outputs of a couple of comparators CP1 and CP4 for normal operation and comparators CP2 and CP3 for a drop state are led to those output AND circuits through respective OR circuits OR-1 and OR-2 and (n) stages of 1-bit shift registers Da-1-Da-n and Db1-Db-n. Consequently, practically accurate signal level discrimination is performed through the simple circuit constitution.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a digital signal level identification method for preventing the occurrence of error bits due to fluctuations in signal level prior to decoding of a reproduced digital signal, and in particular to a digital signal The digital signal level can be accurately identified by following rapid signal level fluctuations.

[Prior art]

This type of digital signal level identification method is used, for example, when reproducing and decoding a digital signal of interleaved NRZI recording recorded magnetically at high density in a digital VTR, error bits may occur due to signal level fluctuations occurring in the magnetic recording and reproducing system. Conventionally, a circuit device having a configuration as shown in FIG. 2 has been used. In other words, the digital signal of interleaved NRZI recording commonly used in digital VTRs is
If you look at every other bit, there is a regularity, and one of the bits has an arbitrary number of 0's, and the values are °°-1' and '+1'.
The input digital signal DS having such a configuration is supplied to the inverting amplifier RA, and the "-1" in the above-mentioned bit array is also changed to "+1".
The original '+i' bit is 10 outputs, and the inverted '+1' is taken out as a - output. The ten outputs and one output of the inverting amplifier RA are connected to a comparator with a latch, CPI.
and CF2 as respective level identification targets, and a sampling switch-S that opens and closes according to the clock CL to timely sample the input digital signal.
WI and SW2 and rectifier diodes RDI and R
The capacitor C is charged to the °' + 1" level of the input digital signal waveform through each D2. The terminal voltage corresponding to the "+1" level of the capacitor C charged in this way is applied to the potentiometer VR to approximately 1 /2 and supplies it to the comparators CPI and CF2 as a comparative reference voltage indicating the threshold for level discrimination.Therefore, depending on whether the input digital signal waveform is above or below this reference voltage, a signal of l゛ or “°0゛” is generated. The level can be identified. That is, the comparison reference voltage was set to 172, which is the rectified value of the input digital signal waveform peak level.

〔problem〕

However, for example, if the reproduced digital signal level suddenly fluctuates due to changes in the operating state of the magnetic recording/reproduction system or fluctuations in the power supply voltage, etc., and especially if the signal level suddenly decreases, the peak level at which the capacitor C is charged is Even if the rectified value of the comparator CPI
, 'The reference voltage level of the level discrimination threshold supplied to CP2 is set so that the discharge time constant of the capacitor C does not change even if the digital signal continues for about 0'' or 10 bits, the reference voltage level does not change. 30 bit period
Since the length is set to about 100 times longer, it is not possible to deal with sudden fluctuations in the input digital signal level.

Therefore, when the signal level suddenly decreases, the input digital signal's +1" or "+1++"
There was a drawback that 1'' was mistakenly identified as 0''.

[Purpose of the invention]

It is an object of the present invention to eliminate the above-mentioned conventional drawbacks and to provide a signal that can be used even when the signal level of an input digital signal fluctuates rapidly.
It is an object of the present invention to provide a digital signal level identification method that changes a threshold voltage level for signal level identification in accordance with the fluctuation of the signal level, thereby making it possible to perform accurate signal level identification.

[Summary of the invention]

That is, in identifying the signal level of a digital signal, the digital signal level identification method of the present invention sets a plurality of identification threshold levels, and provides a plurality of level identification means corresponding to each of the identification threshold levels,
In addition to supplying digital signals in parallel to those level identifying means, the bit array of the digital signal whose signal level has been once identified by any one of the plurality of level identifying means is applied to the digital signal. When an error bit is detected based on the regularity of the beat arrangement, the error bit is corrected by switching the level identification means according to the result of the error bit detection. It is.

[Structure of the invention]

The present invention will be described in detail below with reference to the drawings.

First, the operating principle of the digital signal level identification method of the present invention will be explained with reference to examples of signal waveforms at successive stages of the signal level identification process shown in FIG.

For example, interleave NR commonly used in digital VTRs
As mentioned above, in the digital signal of the ZI recording method, the bits at every interval contain an arbitrary number of "0"s.
Since the bit array has a regularity in which +tH and °゛-1°'' are arranged alternately, the bit array of the digital signal obtained as a result of signal level identification has a regularity that deviates from the regularity. If there is a bit, that bit is an error bit based on signal level fluctuations, so the reference voltage level used as the standard for signal level comparison is changed to match the signal level fluctuations at the location where the error bits occur, and the signal level is adjusted accordingly. The operating principle of the identification method of the present invention is to perform the identification again and correct the signal level identification result.

In other words, the identification signal of the digital VTR is as shown in Fig. 1 (A).
As shown in Figure CB), '-1' and '+1' are generated alternately for the recorded signal of 1. The interleaved NRZI digital signal to be identified is analyzed as described above with reference to Figure 2. Assume that a signal level identification output waveform as shown in FIG. 1(C) is obtained as a result of comparison with a reference voltage set to approximately 1/2 of the peak level of the input digital signal waveform at a normal signal level. In this identification result, in the first half of the bit array, 2
'-1' is continuous after 0°°, and
In the bit array, °' +
1'' are consecutive, and both of them have lost the regularity of the bit arrangement described above.Therefore, two “OII” in the first half of the bit arrangement and 4 “OII” in the latter half
Each one of the “0°′” is “” + 1
” and “−1 pa, the regularity of the bit arrangement will be restored.

Note that in the interleaved NRZI digital signal waveform shown in the figure, only every other odd bit is
1Q11% is represented by "+i", "-1', and every other even bit is represented by ゛·°'. In addition, in the signal level identification circuit shown in FIG.
The input signal level is also converted to "+1" and compared with a reference voltage corresponding to "+1/2" to identify the input signal level, so if there is a change in the DC level of the input digital signal waveform, , '+' of the original input digital signal waveform
An error in level identification does not occur simultaneously on the 1" side and the °'-1" side. That is, for example, if the reference voltage is too high for the °'+1'' side of the original signal waveform where the DC level has decreased, the reference voltage will be
The level is too low for the 1'' side, and even if an error occurs in level identification, it will only occur on either the +1'' side or the -1'' side.

Therefore, when the signal level fluctuates up and down in the input digital signal waveform shown in FIG. 1(B), if the relatively high reference voltage is lowered and level identification is repeated, Suppose that a bit array as shown in D) is obtained. The bit array in (D) of the same figure is
) array, the two “0’s” mentioned above in Figure (C) are
゛ and the latter four °“O′°, each *−
1 “°” and “0°” with “ ” * 2 ” are respectively “ + 1 ” and − in the same figure (D).
It is 1'. Therefore, assuming that this level identification result in FIG. 5(D) is an accurate level identification result that follows the input signal level fluctuation, among the bit arrays in FIG.゛0 with °
If `` is corrected according to the corresponding bit of the bit arrangement of 1ffl (D), the beat/beat arrangement of FIG.

In the level identification method of the present invention, in order to perform the above-mentioned error correction on the bit array of the level identification result, for example, a reference signal corresponding to approximately 1/2 of the peak level at the normal signal level of the input digital signal is used. Regarding the bit array shown in Figure 1 (C), which is the result of signal level identification using voltage, the bit array that is continuous starting from 0゛' is -
At the time when 1”° is detected, and at the time when continuous °° + 1″ is detected after θ°°, the same figure (E)
As shown in the figure, the error detection output "l" is generated and the reference voltage is switched.
Among the bit arrays shown in D), the first detected l°' of opposite polarity going back from the time of error detection, that is, "+1" and "-1'" shown in FIG. By incorporating the bits of the level identification result into the bit array of the same figure (C), as shown in the same figure (CG), the signal level identification result with the error bits corrected (B
) to obtain the same bit array.

〔Example〕

FIG. 3 shows an example of a circuit configuration in which the conventional digital signal level identification circuit shown in FIG. 2 is improved so that the method of the present invention can be implemented according to the above-described operating principle. In the illustrated configuration example, as is clear from the comparison with the conventional configuration shown in FIG.
is inverted to ``11'' and taken out, and supplied to a pair of comparators CP together with a reference voltage set to approximately 1/2 of the peak rectified value of the input signal waveform.
The basic structure for extracting the result of signal level discrimination between "-1" and "-1" converted to "-1" via the OR circuit OR is the same as before. However, in preparation for signal level fluctuations caused by the signal transmission system, especially signal level drops that occur in many cases, a point inserted in the discharge circuit of capacitor C that charges the reference voltage to the peak rectified value when the input signal level is normal is used. The tensiometer VRI is set to approximately 1/2 of the peak rectified value, and the potentiometer VR2 additionally inserted in the discharge circuit of the capacitor C is set to 0.2 of the peak rectified value.
A conventional method in which a reference voltage when the signal level drops is set as low as ~0.4, and a pair of comparators CP2 and CR2 that supply the reference voltage when the signal level drops is replaced with a reference voltage when the signal level is normal. The comparators CPI and CPI for when the signal level is normal are arranged in parallel with the pair of tomparators CPI and CP4 as shown in FIG. Signal level identification error correction configured in multiple stages according to the number of consecutive 0's immediately before bit error detection so that the level identification output of CF2 is switched to the level identification output of comparators CP2 and CR2 for when the signal level drops. The circuit is inserted between the comparator CPI-CP4 and the OR circuit DRb at the output end.

In addition, in both the bit error detection circuit and the signal level identification error correction circuit described above, in order to delay bits in pairs with every other bit when performing bit delay for error detection, a shift register Da of 1 bit is used. and Db are combined into a 2-bit unit delay circuit.

The bit error detection circuit consists of the circuit portion shown surrounded by a dashed line in FIG. 3, and according to the operating principle described above in FIG. ′
The apparatus is configured to detect error bits based on deviations from the regularity of the arrangement. In other words, when the input signal level is normal, “I
The level discrimination output "III" of the comparator CPI for III discrimination is guided to the shift registers Da and Db via the OR circuit ORa, and appears at its output terminal with a delay of 2 bits. When the level identification output is "0", the level identification output of the comparator CP4 for identifying "-1°" when the input signal level is normal is also 0 "', so the output of the two-man power inverting AND circuit ADH becomes 1", Since the next AND circuit AD conducts,
"l" of the shift registers Da and Db outputs are fed back to the inputs of the shift registers Da and Db via the AND circuit AD and the OR circuit ORa, so that the level identification output of the comparator CPI once becomes °°1°'. As long as °゛O°'' continues after this, the state of the level identification output °゛1°' is repeatedly held. Furthermore, when the -1° level identification output of comparator CP4 becomes "1" after the level identification output "l" of comparator CPI, the level identification output of comparator GPI becomes "1".
0゛, and the output of the two-man power inverting AND circuit ADH becomes °0.
'', the next AND circuit AD closes and its output becomes 0, and both OR circuits ORa's output becomes 0, and the inputs of shift registers Da and Db become 0.
is flared. In other words, the level identification output of comparator CPI, C:P4 when the input signal level is normal is °'
When the signal becomes '-1' after 1'' and the regularity is maintained, the bit error detection circuit is cleared.

However, when "°l" comes again after °l in the level identification output of the comparator CPI and the regularity is lost, the last "1" is detected with a delay of 2 bits by shift registers Da and Db. At the same time as reaching the output AND circuit ADa, the next "1" reaches the same AND circuit ADa, so the output of the AND circuit ADa becomes 1", and the AND circuit ADbi2 in the first stage of the level identification error correction circuit described above Inverting input and AND circuit Anal
The detection output "'1" is applied to -2, the former closes and the latter opens, and is supplied to the AND circuit ADb1-2 of the latter, and when the signal level drops, the comparator CP for identifying "-1"
If the 2-bit delayed level identification output of No. 3, that is, the level identification output 2 bits before the detection of regularity loss, is “1”, the next the comparator CP at the same timing, as described above with reference to FIG.
It replaces the level identification output that can be considered as an error in No. 4 and progresses through the level identification error correction circuit toward the output end, mixed with the level identification output of the comparator (: Pl, CR2) at another timing.

Therefore, when the error detection output °"1" of the detection output AND circuit ADa in the bit error detection circuit is led in parallel to the AND circuits Anal-2 and ADbl-3 in the first stage of the level discrimination error correction circuit, If the level identification output of the comparator CP3, which is similarly led in parallel to the AND circuit, is '0''', the AND circuit ADal-2 is not conductive, and therefore the above-mentioned level identification No shuffling of outputs takes place. However, the AND circuit ADbl-3 is conductive because "0" is introduced to its inverting input, and the bit error detection output "1" passes through the AND circuit ADbi3 and the similar AND circuit ADa2- 2 and ADb2-3, and the level identification output is replaced in the next stage as described above for the first stage.Therefore, the level identification output of comparator CP3, which is traced back by 2 bits from the time of bit error detection, is Bit error detection output “
1'' is sequentially sent to the subsequent stage, and the level identification error correction is performed by replacing the level identification outputs as described above, going back until the level identification output of the comparator CP3 becomes ``°l°°''. Note that since the number of consecutive "0"s in the level identification output is usually less than 10, it is sufficient to cascade about 10 stages of level identification output switching as described above in the level identification error correction circuit.

On the other hand, when the regularity is lost, in which the level discrimination output "1" of the comparator CP4 for discriminating the normal signal level "-1" is supplied twice to the bit error detection circuit described above, the second " When the level identification output ``1°'' of the -1'' identification output comparator CP4 is led to the detection output AND circuit ADb, the first ``l I
゛+1°' identification comparator C corresponding to + identification output
Same as PI level identification output ``0''', 1 bit before 2 bits.
The output "0" of the AND circuit AD from which the output "o" of the 2-inverting input AND circuit ADH, to which the second "-1" identification output "1" is applied to the inverting input, and the output "0" of the AND circuit AD are simultaneously supplied to the OR circuit ORa. , the output "0°" of the OR circuit ORa is delayed by 2 bits by the shift registers Da and Db and is simultaneously led to the inverting input of the detection output AND circuit ADb, so that the bit error detection output II is output from the AND circuit A[lb.
I I+ is taken out and the AND circuits Anal-1, ADbl-1, AD in the first stage of the level identification error correction circuit
bl-4 in parallel, and level identification error correction is performed between comparators CP1 and CR2 by exchanging the level identification outputs in the same manner as described above for two consecutive detections of +1°.

Next, a digital signal level identification system in which the circuit configuration of the level identification error correction circuit in the level identification circuit having the configuration shown in FIG. An example of the circuit configuration is shown in FIG. The configuration example shown in FIG. 4 is completely the same as the configuration example shown in FIG. The multivibrator MV is commonly connected via the OR circuit ORC.
and the time constant circuit R of the multi-by-break MV.
Once the bit error detection output “1'' is supplied to the multi/habulator MV by setting @Ca appropriately,
For a period of about 10 bits, the Q output of the multi-by-break MV is connected to the 1++ level, and the Q output "1°" is connected to the inverting input of the output AND circuit ADbn of the significantly simplified level identification error correction circuit and the other The output AND circuits ADbn and ADan are supplied with a comparator pair CPI for when the signal level is normal.

Comparator CP2 for CR2 and signal level drop
．． 1-bit shift registers Da-1, Da-2, . . . -, Da-n and Dbl in which the level identification output of CP3 is continuously connected to each OR circuit 0R-1 and 0R-2 and 8 stages
, Db2.・.

Db-n, respectively. Therefore, while the AND circuit ADbn is non-conductive for the bit error detection output "t", the AND circuit ADan is conductive, and the comparator CP2 is exclusively used when the signal level drops during the n-bit period after the bit error detection.

The level identification output of CF2 is taken out as an error-corrected level identification output digital signal. Therefore, as is clear from the above description of FIG. 1, the significant logic level output "+1'" or
The occurrence of serious errors in digital signal level identification in the direction of identification can be avoided to a large extent.

Note that the digital signal level identification using the method of the present invention is as follows:
The present invention is not limited to the above-mentioned example by combining level identification means such as handling alternate bit signal combinations differently or handling "II 11" and "-1" differently. The present invention can be practiced with numerous modifications within the scope of the gist.

〔effect〕

As is clear from the above description, according to the present invention, even when signal level fluctuations occur in a magnetic recording/reproducing system such as interleaved NRZI recording digital signals commonly used in digital VTRs, especially when the signal level decreases rapidly, A corresponding reduction in the level discrimination threshold provides effective error protection, in particular the elimination of so-called missing errors in which significant bits of +1° or -III are erroneously identified as "0"°.

In particular, if the signal level identification method 6' of the present invention is implemented using the circuit configuration shown in FIG. Since these are treated separately, bit error detection and signal level identification errors can be detected extremely accurately.On the other hand, if the signal level identification method of the present invention is implemented using the circuit configuration shown in FIG. Although the effect is limited to the extent to which . It is also expected that the signal level identification method of the present invention can be implemented using an intermediate circuit configuration that combines both circuit configurations.

Note that the digital signal level identification method of the present invention can be applied not only to the above-mentioned interleaved NRZI method but also to digital signals of the NRZI method (partial response (1, -1) method) to obtain similar effects. In the latter method, unlike the former method, there is no regularity of every other bit, so the bit delay in units of 2 bits, which was done in the former method, is changed to units of 1 bit.
Exactly the same signal processing can be performed.

As a result of actual measurements by incorporating a digital signal level identification circuit with the circuit configuration shown in Figure 3 into a 43 megabit/second digital VTR, a small number of slightly erroneous bits (B/) remained among the 2730 bits of the l block. The number of error blocks has been reduced to 1/2 to 1/4 compared to the conventional method.

Therefore, although it is ineffective against long-term 8-strike errors caused by dropouts that occur in digital VTRs, the method of the present invention is particularly effective in correcting and eliminating isolated error bits caused by short-term fluctuations in signal level. A remarkable effect can be obtained.

[Brief explanation of drawings]

1 (A) to (G) are signal waveform diagrams sequentially showing the operating principle of the digital signal level identification method of the present invention; FIG. 2 is a block diagram showing the configuration of a digital signal level identification circuit according to the conventional method; FIG. 3 is a block diagram showing an example of the configuration of a digital signal level identification circuit according to the method of the present invention, and FIG. 4 is a block diagram showing another example of the configuration of the digital signal level identification circuit. RA...Inverting amplifier, SWI, SW2...Sampling switch, VR,
VRI, VR2... Potentiometer, C, C:a
...Capacitor, RDI, RD2... Rectifier diode, CPI ~CP
4... Comparator with latch, Dia-j, Dib
-j, Da, Db -1 bit shift register, ADbi-j...1 manual inversion AND circuit,
10R, ORa, ORb, ORc, 0Ri-j
-OR circuit, R...resistor, MV...multivibrator. Patent applicant Japan Broadcasting Association representative
Person Patent Attorney Yoshi Tani −○
○ 0 0 00 0 0
−〇〇゛ 0 0 0
0-7 '----7 000T O -Work ^ ^ ・, +

Claims (1)

[Claims] To identify the signal level of a digital signal, multiple levels of identification threshold levels are set, a plurality of level identification means corresponding to each of the identification threshold levels are provided, and the digital signal is connected to the level identification means in parallel. At the same time, error bits are added to the bit array of the digital signal whose signal level has been identified by any one of the plurality of level identifying means based on the regularity of the bit array of the digital signal. 1. A digital signal level identification method, characterized in that, when detected, the error bit is corrected by switching the level identification means according to the result of detecting the error bit.