JPS61134123A - Bias oscillating circuit of tape recorder etc. - Google Patents

Bias oscillating circuit of tape recorder etc.

Info

Publication number
JPS61134123A
JPS61134123A JP25577584A JP25577584A JPS61134123A JP S61134123 A JPS61134123 A JP S61134123A JP 25577584 A JP25577584 A JP 25577584A JP 25577584 A JP25577584 A JP 25577584A JP S61134123 A JPS61134123 A JP S61134123A
Authority
JP
Japan
Prior art keywords
oscillation
circuit
voltage
set value
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25577584A
Other languages
Japanese (ja)
Inventor
Kazuhiko Iwabuchi
岩尅 一彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marantz Japan Inc
Original Assignee
Marantz Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marantz Japan Inc filed Critical Marantz Japan Inc
Priority to JP25577584A priority Critical patent/JPS61134123A/en
Publication of JPS61134123A publication Critical patent/JPS61134123A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To maintain an oscillation output stably over a wide range of voltage by connecting a controlling transistor between the middle point of two oscillation coupling transistors constituting an oscillating circuit and the power source terminal, and connecting a rectifier circuit that detects the outlet level to an output terminal of the oscillating circuit. CONSTITUTION:When voltage V(o) of output terminal N of the oscillating circuit becomes lower than a set value, current in the rectifier circuit D decreases proportionally, and increases resistance between collector and emitter of a transistor 5. Thereby, voltage drop in a bias resistance R10 decreases and current that flows to the base of a controlling transistor Q increases, and voltage V(CE) between collector and emitter of Q becomes low and effective power source voltage becomes high and the oscillation output V(o) is returned to the set value. In the case where the V(o) becomes higher than the set value, current in the rectifier circuit D increases proportionally, and V(E) of the controlling transistor Q is made higher by reverse operation. The effective power source voltage of an oscillating circuit A is lowered, and consequently, the oscillation output V(o) is suppressed and returned to the set value.

Description

【発明の詳細な説明】 産業上の利用分野: 本発明は、テープレコーダ等、の
バイアス発振回路に関し、特に発振回路の出力を安定さ
せたバイアス発振回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application: The present invention relates to a bias oscillation circuit for tape recorders and the like, and more particularly to a bias oscillation circuit that stabilizes the output of the oscillation circuit.

従来の技術: バイアス発振回路の出力を安定させる為
に従来は、まず電源に対して電源安定回路を組合せ、次
に、機械的スイッチないし電子スイッチで操作するバイ
アス切換回路を接続し、これらの回路動作の下でバイア
ス発振回路が安定に動作するようにしていた。しかしな
がら、バイアス発振回路の効率によって発振出力が変化
する結果を招き1.また、電池使用の場合には低電圧に
対する安定化が困難になって発振の安定を保持すること
が難しくなるのが実情である。
Conventional technology: In order to stabilize the output of a bias oscillation circuit, conventionally, a power supply stabilization circuit was first combined with the power supply, then a bias switching circuit operated by a mechanical or electronic switch was connected, and these circuits The bias oscillation circuit was made to operate stably under the operating conditions. However, the oscillation output may change depending on the efficiency of the bias oscillation circuit.1. Furthermore, in the case of using a battery, it is actually difficult to stabilize the oscillation at low voltages, making it difficult to maintain stable oscillation.

本発明が解決しようとする問題点: 従来技術が行って
いた供給電圧を安定化させる技術的思想では、バイアス
発振回路の動作条件としてX実際的な有効電源電圧によ
って動作させる思想を欠(から、発振出力がバイアス発
振回路の効率によって変化するという従来技術の不満点
を解消した時の有益性同様に、この基本的な回路思想の
盲点の解消を本発明で行う。
Problems to be solved by the present invention: The technical idea of stabilizing the supply voltage, which has been practiced in the prior art, lacks the idea of operating the bias oscillation circuit using a practical effective power supply voltage as an operating condition. Similar to the benefit of solving the disadvantage of the prior art that the oscillation output varies depending on the efficiency of the bias oscillation circuit, the present invention solves this blind spot in the basic circuit concept.

問題点を解決する為の手段二 本発明の技術は、発振回
路を構成する発振結合トランジスタ1.2の間の中間点
と電源端との間に制御トランジスタQを接続する一方、
該発振回路の出力端に出力レベルを検出する整流回路を
接続し、該整流回路の出力で前記制御トランジスタQを
動作させるバイアス発振回路の構成にある。
Means 2 for Solving the Problem The technology of the present invention connects a control transistor Q between an intermediate point between oscillation coupling transistors 1 and 2 constituting an oscillation circuit and a power supply end, while
The bias oscillation circuit is configured such that a rectifier circuit for detecting the output level is connected to the output end of the oscillation circuit, and the control transistor Q is operated by the output of the rectifier circuit.

作用: 発振回路の出力レベルV (o)に対して、■
(0)が低下した時整流回路を介する信号により制御ト
ランジスタQの抵抗を低下させて発振回路の有効電源電
圧を高(し、出力レベル■(0)を設定値に戻す。出力
レベルV (o)が設定値より高くなった時、制御トラ
ンジスタQの抵抗が増大するように整流回路を介する信
号によって制御トランジスタの制御電圧を下げ、これに
より発振回路の有効電源電圧を直接低下させて設定値の
■(0)に戻させる。電源からは発振回路に対して常時
有効電源電圧が供給されて発振出力を安定させる。これ
により従来より広い電圧域で発振を行わせることができ
る。
Effect: For the output level V (o) of the oscillation circuit, ■
(0) decreases, the resistance of the control transistor Q is lowered by a signal via the rectifier circuit, the effective power supply voltage of the oscillation circuit is increased (and the output level (0) is returned to the set value.The output level V (o ) becomes higher than the set value, the control voltage of the control transistor is lowered by a signal via the rectifier circuit so that the resistance of the control transistor Q increases, and this directly lowers the effective power supply voltage of the oscillation circuit to reach the set value. (2) Return to (0).The power supply always supplies an effective power supply voltage to the oscillation circuit to stabilize the oscillation output.This allows oscillation to occur in a wider voltage range than before.

実施例: 図面の発振回路Aの場合は、発振結合トラン
ジスタ1.2の中間点Mと電源マイナス端ES2との間
に制御トランジスタQを直列に接続し、電源プラス端B
SIを同発振回路Aのコイル3の一次側に接続した例で
ある。この出力端Nに接続された応用(負荷)回路部B
はテープレコーダの録音ヘッドH1、R2、R3を持つ
。R1−R6は抵抗で、C1〜C3はコンデンサである
。整流回路りはここでは出力端Nのプラス端に抵抗R7
−ダイオード4−コンデンサC4−アースを直列に接続
して、発振出力の一部を検波し平滑する。コンデンサC
4に並列に発振強度調整用抵抗R8、R9を接続し、両
抵抗中間点に制御端を接続したトランジスタ5と続され
る。
Example: In the case of the oscillation circuit A shown in the drawing, a control transistor Q is connected in series between the midpoint M of the oscillation coupling transistor 1.2 and the negative power supply terminal ES2, and the positive terminal B of the power supply
This is an example in which the SI is connected to the primary side of the coil 3 of the oscillation circuit A. Application (load) circuit section B connected to this output terminal N
has recording heads H1, R2, and R3 of a tape recorder. R1-R6 are resistors, and C1-C3 are capacitors. Here, the rectifier circuit has a resistor R7 at the positive end of the output terminal N.
- Diode 4 - Capacitor C4 - Ground are connected in series to detect and smooth a part of the oscillation output. Capacitor C
Resistors R8 and R9 for adjusting oscillation intensity are connected in parallel to transistor 5, and the control end is connected to the midpoint between the two resistors.

制御トランジスタQの制御端と電源端ESIの間に録音
スイッチ6と制御用バイアス抵抗RIOを接続し、トラ
ンジスタ5の動作を可変抵抗器のように利用する。発振
結合トランジスタ1.2の中間点Mと電源端ES2の間
に接続した制御トランジスタQは整流回路りの出力に対
応して動作する。
A recording switch 6 and a control bias resistor RIO are connected between the control terminal of the control transistor Q and the power supply terminal ESI, and the operation of the transistor 5 is used like a variable resistor. A control transistor Q connected between the intermediate point M of the oscillation coupling transistor 1.2 and the power supply terminal ES2 operates in response to the output of the rectifier circuit.

発振回路出力端Nの電圧v(0)が設定値より低くなっ
た時、整流回路りの電流がこれに比例して減少しトラン
ジスタ5のコレクターエミッタ間抵抗を増加させ、これ
によってバイアス抵抗R10での電圧降下が減少し制御
トランジスタQのベースに流れる電流が増加し、Qのコ
レクターエミッタ間電圧V (CE)が低くなって発振
回路Aの有効電源電圧が高くなり、発振出力■(0)を
設定値に戻す。■(0)が設定値より高くなった場合は
、整流回路りの電流がこれに比例して増加し、逆の動作
により制御トランジスタQのV (CE)が高くなって
発振回路Aの有効電源電圧を下げ、この結果発振出力v
(0)を抑えて設定値に戻す。
When the voltage v(0) at the output terminal N of the oscillator circuit becomes lower than the set value, the current in the rectifier circuit decreases in proportion to this, increasing the collector-emitter resistance of the transistor 5, which causes the bias resistor R10 to The voltage drop in the control transistor Q decreases, the current flowing to the base of the control transistor Q increases, the collector-emitter voltage V (CE) of Q decreases, the effective power supply voltage of the oscillation circuit A increases, and the oscillation output ■(0) increases. Return to set value. ■When (0) becomes higher than the set value, the current in the rectifier circuit increases in proportion to this, and due to the reverse operation, the V (CE) of the control transistor Q increases, causing the effective power supply of the oscillation circuit A. The voltage is lowered, resulting in the oscillation output v
(0) to return to the set value.

電池電源のテープレコーダのバイアス発振回路に本発明
を用いた場合、電圧増減に対する従来の電圧安定手段が
安定電圧を出せない条件でも安定した発振を出すことが
できる。
When the present invention is applied to a bias oscillation circuit of a battery-powered tape recorder, stable oscillation can be produced even under conditions where conventional voltage stabilizing means against voltage increases and decreases cannot produce a stable voltage.

発振回路Aと電源BSとの間に備える制御トランジスタ
Qと、発振回路Aの出力端Nに接続した整流回路りとの
組合せ態様は、この実施例に限定されない。整流回路り
の信号量は発振出力V (。
The combination of the control transistor Q provided between the oscillation circuit A and the power supply BS and the rectifier circuit connected to the output terminal N of the oscillation circuit A is not limited to this embodiment. The signal amount of the rectifier circuit is the oscillation output V (.

)に対応し、この信号に対応して制御トランジスタQが
V (o)を設定値に安定させるように動作する回路態
様は公知技術から適宜選択できるものである。
), and the circuit configuration in which the control transistor Q operates in response to this signal to stabilize V (o) at the set value can be appropriately selected from known techniques.

効果二 制御トランジスタQは、発振回路Aの発振出力
V (o)に対応する整流回路りの出力によって、■(
0)が低下する時は発振回路Aの有効電源電圧を高くし
てV (o)を設定値に戻し、またV (o)が増加す
る時には同有効電源電圧を下げてv(0)を設定値に戻
させるから、従来必要とされた供給電圧の安定化手段を
不要とする外、発振出力電圧を切換える場合にも発振回
路の効率に関係無く自在に切換えることができ、従来よ
りも広い電圧域に対して発振出力を安定保持することが
できる。
Effect 2: The control transistor Q is controlled by the output of the rectifier circuit corresponding to the oscillation output V (o) of the oscillation circuit A.
0) decreases, increase the effective power supply voltage of oscillation circuit A to return V (o) to the set value, and when V (o) increases, lower the same effective power supply voltage to set v (0). This eliminates the need for stabilizing the supply voltage, which was required in the past, and allows the oscillation output voltage to be switched freely regardless of the efficiency of the oscillation circuit, allowing for a wider voltage range than before. The oscillation output can be kept stable over the range.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の一実施例を示す概略回路図である。 A:発振回路   B:応用回路部 D:整流回路   Q:制御トランジスタESI −E
S2 :  電源 1.2:発振結合トランジスタ 5:トランジスタ
The drawing is a schematic circuit diagram showing one embodiment of the present invention. A: Oscillator circuit B: Application circuit D: Rectifier circuit Q: Control transistor ESI-E
S2: Power supply 1.2: Oscillation coupling transistor 5: Transistor

Claims (1)

【特許請求の範囲】[Claims] 発振回路を構成する発振結合トランジスタ1、2間の中
間点と電源端との間に制御トランジスタQを接続する一
方、該発振回路の出力端に出力レベルを検出する整流回
路を接続し、該整流回路の出力で前記制御トランジスタ
Qを動作させることを特徴とするテープレコーダ等のバ
イアス発振回路
A control transistor Q is connected between the midpoint between the oscillation coupling transistors 1 and 2 constituting the oscillation circuit and the power supply terminal, while a rectifier circuit for detecting the output level is connected to the output terminal of the oscillation circuit. A bias oscillation circuit for a tape recorder, etc., characterized in that the control transistor Q is operated by the output of the circuit.
JP25577584A 1984-12-05 1984-12-05 Bias oscillating circuit of tape recorder etc. Pending JPS61134123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25577584A JPS61134123A (en) 1984-12-05 1984-12-05 Bias oscillating circuit of tape recorder etc.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25577584A JPS61134123A (en) 1984-12-05 1984-12-05 Bias oscillating circuit of tape recorder etc.

Publications (1)

Publication Number Publication Date
JPS61134123A true JPS61134123A (en) 1986-06-21

Family

ID=17283450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25577584A Pending JPS61134123A (en) 1984-12-05 1984-12-05 Bias oscillating circuit of tape recorder etc.

Country Status (1)

Country Link
JP (1) JPS61134123A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302903A (en) * 1989-05-17 1990-12-14 Matsushita Electric Ind Co Ltd Recording bias circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4725960U (en) * 1971-04-20 1972-11-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4725960U (en) * 1971-04-20 1972-11-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302903A (en) * 1989-05-17 1990-12-14 Matsushita Electric Ind Co Ltd Recording bias circuit

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