JPS61131298A - Non-volatile memory circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous writing due to an external noise of a static electricity, etc., by connecting prescribedly a voltage limit element, an electric current limit element, etc. CONSTITUTION:To non-volatile memories 201, 202... between a terminal for electric power source voltage VDD or VSS and a terminal for high electric power source VDD of negative for writing, an electron is poured through a voltage VPP,and the writing is executed. Between these terminals, voltage control elements 203 and 204 are connected and electric current limit elements 206, 205, etc., of a transistor, a coil, etc., are connected between the terminal and the memories 201, 202... to which the voltage VPP is supplied, the electron to the memories 201, 202... due to the external noise of a static electricity, etc., is not poured, and the erroneous writing due to the external noise can be prevented.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an IP ROM (Brasable Pro
grammable ROM), K K FROM
(Blectrical Erasable Pro
The present invention relates to improvements in a circuit for writing data from the outside into a ROM and a circuit for erasing data in an electronic integrated circuit in which a ROM is formed on the same chip.

rPrior art] Figure 1 shows an FA built in an integrated circuit for an electronic watch.
M OS (Floating-crn,te
Ava, 1anchain, iectAonMO8
) is the write entry path of a conventional FiPROM.

Connect A and B terminals to VTITl= [I J , Vss=
ro J and set V to vTID.
When a high negative voltage is applied to PPK, the FAMO8Icg element connected in series with the transistor set to "0" is injected (103 and 104 are FAMO8).

Since the injected electrons can be retained semi-permanently, FAMO
8 can be a writable semiconductor memory.

However, if the circuit shown in Figure 1 is built into the electronic watch integrated circuit, the drains of F
Since it was set to pp, there was a drawback that electrons could be erroneously injected into the FAMO 8 when external noise or thunder and lightning were added.

〔the purpose〕

The purpose of the present invention is to transmit FAMO8K without limiting the high voltage required for writing and erasing, and
To provide a write circuit and a write/erase circuit that limit normal voltage and current against external noise such as static electricity,
Al.

〔overview〕

FIG. 2 is a block diagram 201.
Reference numeral 202 denotes non-volatile memory, and a required number of non-volatile memories are arranged in the same structure. 203. 204 is a voltage limiting element VI'ID
Alternatively, it is arranged in parallel to the vsS terminal and the ypp terminal, and when a high voltage exceeding the required write voltage and erase voltage is applied, it serves to limit the high voltage. Voltage limiting elements include resistors, transistors, diodes, capacitors, and the like. Further, 205 and 206 are elements for limiting current with a steep slope or a slight slope, and are arranged in series between the ypp terminal and the nonvolatile memory. The current limiting element may be a resistor, a transistor, a coil rC, or the like. By providing the voltage limiting element and the current limiting element in this way, it is possible to prevent erroneous writing and erasing.

FIG. 4 shows another embodiment according to the invention. The voltage limiting element is composed of a P -N diode and P -N capacitors 606 to 608. The current limiting elements are high voltage MOS transistors 409 and 410. The diode 405 performs N- concentration control for diodes that are normally formed parasitically on integrated circuits.
Reduces reverse breakdown voltage. The breakdown pressure in the reverse direction is set to about -15V, which is within the normal write voltage range. In this way, when external noise with a relatively large proportion of DC components is applied,
The peak level force is cut to about 15 V. The voltage that has been cut is the voltage below the normal write range, so unless the transistors 401 and 402 are ONL, F
'The gates of the AMOs 8403 and 404 are never charged. High voltage transistors excluding diodes,
Role of capacitor and low-pass filter □
fulfill.

FIG. 3 shows an embodiment according to the present invention. DC resistance 305 by P-well as a current limiting element. 306 and parasitic inductance due to aluminum wiring 307.30
Use 8. In addition, a capacitor based on p+-NIC is used as a voltage limiting element. With such an arrangement, a low-pass filter can be configured, and high frequency components caused by external noise, static electricity, etc. can be removed. When actually writing data, it is necessary to apply high pressure for a longer time constant than before installing these protection circuits, but this is only about a few m5ec and does not pose a problem.

The structure of a low-pass filter is made up of resistance and capacitance, inductance and capacitance, etc., but in winter there are cases where just one pair is insufficient to remove high frequency components as a filter.
In reality, it is used in layers. Figure 3 shows a two-stage configuration, but the more stages are stacked, the more the voltage drop h due to resistors 305 and 306.
It is preferable to design the number of stages in consideration of the frequency spectrum of the write voltage and external noise.

FIG. 5 shows another embodiment according to the invention. Figures 3 and 4
The difference from the figure is that the P channel,
The use of N-channel MOS) transistors,
A time constant circuit consisting of a capacitor 506 and a resistor 507 is useful.

Explaining with reference to FIG. 5, the voltage limiting element is a diode 505, and the manufacturing method and operation are the same as those shown in FIG. N-channel transistor 509 and P-channel transistor 510 are current limiting elements. When writing data, a voltage of about VPPlc-15V is applied. From the gate voltage of the inverter 508 (VDD=OV), the voltage decreases in the negative direction with a time constant composed of 506 and 507. When the threshold voltage of the inverter is crossed, P, N) transistor 510. 509 is ONI,
Therefore, the voltage applied to ypp is FAMO8503, 50
4K transmitted, F A M selected by A and B
Charge is injected into the OS.

Next, when high voltage and short pulses such as electrostatic noise are applied, if the time constant of 507,506 VC is set long, the voltage at the 7 points will not be pulled in the negative direction, and Vl)D
expresses the state of Therefore, P, N transistor 509',
510 is not turned on, and the electrostatic noise added to ypp can be suppressed. In other words, if VPPK is not applied for a certain period of time, that voltage will be applied to the FA which is a memory.
It has a circuit configuration that does not transmit this to MO8.

Next, FIG. 6 shows an example in which the protection circuit of FIG. 5 is applied to an EKPROM. 601 and 602 are selection transistors,
603. This is a memory transistor with a 604-layer gate structure. Data writing is performed as follows.

When writing to 603 A, = Vl)D, A2 =
Transistor 501 e ON #se60 as v8S
Apply +21V to the gate of No.3. Since the upper gate of 603 is +21V and the drain voltage is VSS, lightning and particles accumulate on the floating gate due to the tunnel effect.
The threshold voltage increases. Conversely, if you want to delete, use A, =
VT) D, A2= + 21 V, 603
Apply vSS to the gate and +21V to the drain to release electrons. Erasing can be performed by applying a voltage with a polarity opposite to that of writing. 603. Since 604 is partially thinned only in the thickness between the floating gate and the drain, a tunnel effect is likely to occur.

An EEPROM based on this different principle has high voltage terminals Vllll+1 (+21 V) and 78 V during writing and erasing.
Since no DC circuit can be formed between 8 and 8, only a small amount of energy is required for writing and erasing. Therefore, it is sensitive to external noise and electrostatic noise, resulting in soft errors (erroneous writing and erasing).

Therefore, a protection circuit is required, and the P channel transistor 605 is used as a voltage limiting element, and the P channel transistor 605 is used as a current limiting element.
N) Langistaro10. I use 609 f.

The operation is exactly the same as the ffl8 circuit shown in Figure 5, and the EEF
In the case of ROM, +21V is applied to the ypp terminal for writing, and vss = ov is applied for erasing. Even if Izuwa, 6
10, 609 h″-a certain time h″ to turn on
-- Necessary, within the time constant due to the resistor 607 and capacitor 606): For /l/s, no voltage is transmitted to the gates of the memories 60, 604, etc.

〔effect〕

Non-volatile memory writing circuit K'm v)
As shown in Figure 6, resistors, diodes, transistors, capacitors are used as voltage limiting elements, and resistors, transistors, coils A, etc. are used as current limiting elements. Erroneous writing due to noise generated by the human body and static electricity generated by the human body can be prevented.

[Brief explanation of drawings]

Figure 1... Figure 2 shows a conventional write circuit. Figure 2 is a block diagram of the present invention. Figure 3, Figure 4, Figure 5, Figure 6... Figure 1Q1 shows an embodiment according to the present invention. 101...P channel transistors 103, 104...FAM O5201
, 202...Nonvolatile memory 203, 204
...Voltage limiting elements 205, 206...
-Current limiting elements 301, 302...P channel transistors 503, 304...FAMO
8305, 306, 507, /+07...Resistance 307, 308...Inductance 309
, 310, 506.606...Capacitor 4
01, AO2,409,410...P channel transistor 403.404.503.5n4
...FA↑JO8405, 5n5...
Diodes 406, 407, 408... Capacitors 508, 608... Inverter 50
9.609...N-channel transistor 51
0, 610, 15...P channel transistors 603, 604... Memory transistors with double-layer gate structure [So+

Claims (1)

[Claims] (1) In a MOS integrated circuit for an electronic watch in which a nonvolatile memory is formed on the same chip, a voltage limiting element is disposed between a high voltage application terminal for data writing and a power supply terminal, and a voltage limiting element is arranged between the high voltage application terminal for data writing. A nonvolatile memory circuit characterized in that a current limiting element is arranged between the nonvolatile memory and the nonvolatile memory to prevent intrusion of external noise.