JPS61130990A - Compression reading timing circuit for crt screen information - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a timing circuit for compressing and reading CRT screen information.

[Background of the invention]

For example, screen information such as characters and numbers output as digital signals from a combiator etc. is generally 1'clj
, K can be recognized by a person by being displayed on a CRT screen.

Therefore, let us consider reading screen information directly from digital signals without using a display device such as a CRT.

To read the screen information for one field of the C''RT87 screen, it is necessary to input a digital signal (that is, one screen datan) corresponding to that one field, and then process it. Generally speaking, the screen data equivalent to one field has 25 data columns.
Since it is very long, from 0 to 450, the amount of data to be imported is enormous, and it is actually impossible to process it. Therefore, rather than directly inputting screen data, the screen information is input to a circuit that compresses data called a pattern compression circuit, compresses the screen information, and then processes it to read the screen information. At this time, since the pattern compression circuit starts and stops its operation in response to a start/stop signal from an external source, the timing of the start/stop signal is very long.

So, here's how to get the timing right in the past.

K will be explained using FIGS. 2 and 3.

FIG. 2 is a timing chart for explaining the timing of the conventional start/stop signal, and is an enlarged timing chart showing part A of FIG. 2 of FIG. 3.

In FIGS. 2 and 5, V and 5YNC are vertical synchronizing signals, DATA is screen data, CI is a data clock, and 5TAR'l' and S'rOP are start/stop signals.

As shown in FIG. 2, conventionally, the pattern compression circuit's reading sister track (part A) and V
, the circuit was stopped at the falling edge of 5YNC, and one field's worth of screen data was input.

Generally, the timing of CRT screen information is generated by dividing the frequency of the data clock (CLK), 'l/, 5YNC, H, and 5YNC from one original oscillation clock. However, the branch circuit, buffer, waveform shaping circuit,
After passing through the drive circuit and reaching the connector of the output circuit, the phase and timing relationships will be off at the 9th point in time, especially when the repetition frequency is low, such as V, S'rNC (60Hz), as shown in Figure 6. CLKC with high repeat frequency
This occurs as jitter on the time axis of several tens of MHz) ◇) Therefore, in the timing arrangement described above, the 5TAR'rφS'l'OP signal is 5TART-8'l, which is t+ ahead of the original timing. '0
F-1 or 5TRR'l'・5TO delayed by t2
Unlike P-2, etc., these are clocked in terms of CLK timing. CR'I at these timings
'When the screen data for one field of the screen is pattern-compressed, there is a drawback that the resultant value of the pattern compression changes every time it is read.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a compression read timing circuit that can start and stop the compression operation of a pattern compression circuit at stable and reliable timing.

[Summary of the invention]

Very fast (tens of megabytes) CI, DA'rA,
Timing alignment with low-speed V, 5YNC, H, SMNG, etc. is difficult due to the large circuit scale and development effort, which basically lacks reproducibility and stability. We considered a method to obtain timing directly using DATA timing ◇ As a result, we focused on the fact that there is always DATA on the screen to be read, and that this DA'rA appears in every field (every frame in the case of interlace). , in the present invention, V, arrives first after 5YNC arrives, and 7? The start trigger is applied at the timing of DATA, and the stock trigger is applied at the timing of the first DATA of the next cycle.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIGS. 1 and 4 below.

This will be explained with reference to FIG.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, 6 is a delay circuit, 4 is a 7-digit clock, 5 is a shaping circuit, 6 and 7 are OR gates, 8 is a switch, and 9 is a pattern compression circuit.

As shown in Fig. 1, CRT screen data for high-definition color display is generally used in the 4al types of D-R, D-G, D-B, and D-1 (intensity). In order to obtain the screen data that arrives first among them, these four screen data t'' are input to the OR gate 6, and the logical sum is taken to create the total screen data DI'. Although not directly related to timing generation, the pattern compression circuit 9
◇When reading and reading screen information that is only displayed in monochrome, such as with a word processor, use the OR gate 6 mentioned above.
and the switch 8 are unnecessary.
2 is a timing chart showing an enlarged portion of B in the figure.

In FIGS. 4 and 5, DA'l'A indicates the total screen data output from the OR gate 6.
and Q+ (output of flip-frog 4) shown in Figure 4.
@First, at the falling timing of V and 5YNC, clear the 7th lip to 41 and set q to "L", and then wait for the arrival of the first DATA. Time 1. (After approximately 58 hours or more), the first D via OR gate 7
When ATA arrives, q
, becomes 'H'.Then, the subsequent DA'l'A+7
) In order to prevent Q from changing due to inversion, Q and ft are returned to the terminals of 7 and 70 knobs 4 through an OR gate 7 as shown in Figure 1.6 Qj is the next V, 5YNC fall. ◇Q is divided by 172 in the shaping circuit 5 to create Q2 ◇As a result, (h arrives at the beginning of the first period) D.A.
The signal becomes a 5TART-8'l'OP signal which rises at the TA timing and falls at the same timing of the first period.

(However, S'I'AR'l'-3 of the pattern compression circuit 9
? If you use an OP signal specification different from the above, the line and shaping circuit 5 must match it.0) Also, in Figure 5, the setup from when DATA rises to when it is established is shown. To secure time (tl), C
LK is delayed by the delay circuit 3 shown in FIG. 1 to adjust the phase of both. As a result, when the output signal of the delay circuit 3 is passed as CLK to the pattern compression circuit 9, the pattern compression circuit 9 outputs DATA and CLK.
There is no need to adjust the LK setup time.

〔Effect of the invention〕

According to the present invention, there are first-order effects.

(1) When reading the screen information for one filler of the CRT screen, the repetition frequency is significantly different from V, 5YN (:) when it arrives first without applying an unstable trigger at DA'l'A or CL. By applying the trigger with DATA, stable and reliable timing can be obtained, so it is possible to compress and read screen information with good reproducibility and high reliability.

(21 In the prior art, in order to obtain stable timing, K must return to the CRT screen information generation circuit and take out each basic timing signal and configure a complicated circuit, but according to the present invention, a simple It can be configured with a circuit and can be realized using only the CRT screen information output signal (output to the connector), resulting in a significant cost reduction.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 21 is a timing chart for explaining how to take the timing of a conventional start/stop signal, and Fig. 31 is an enlarged part A of Fig. 2. FIG. 4 is a timing chart for explaining the operation of the present invention, and FIG. 5 is a timing chart showing part B of FIG. 4 in an enlarged manner. Code explanation 5...Delayed path, 4...Flip-flop, 5...
- Shaping circuit, 6, 7...OR gate, 8...switcher, 9...pattern compression circuit. 'jAz口5Ti7P-1

Claims (1)

[Scope of Claims] 1) When serial screen information for one field of CRT screen is input to a pattern compression circuit, compressed and read, screen data that arrives first after the vertical synchronization signal included in the screen information arrives. A timing circuit for compressing and reading CRT screen information, characterized in that the pattern compression circuit starts a compression operation in synchronization with , and stops the same operation at the same timing in the next cycle. 2) In the compression reading timing circuit according to claim 1, when the screen data included in the screen information is composed of multiple types of data coming from multiple parallel systems, such as in the case of color, the logical sum of the data is A timing circuit for compressing and reading CRT screen information, characterized in that the first arriving screen data is obtained from the output.