JPS61128747U - - Google Patents
Info
- Publication number
- JPS61128747U JPS61128747U JP922085U JP922085U JPS61128747U JP S61128747 U JPS61128747 U JP S61128747U JP 922085 U JP922085 U JP 922085U JP 922085 U JP922085 U JP 922085U JP S61128747 U JPS61128747 U JP S61128747U
- Authority
- JP
- Japan
- Prior art keywords
- input
- priority value
- control device
- switch circuit
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の制御装置のプライ
オリテイ値設定スイツチ回路の詳細を示す図、第
２図は本考案の制御装置と入出力装置との接続構
成を示すブロツク図である。
１ａ，１ｂ，１ｃ，１ｄ……入出力装置、２…
…制御装置本体、２ａ，２ｂ，２ｃ，２ｄ……チ
ヤンネルインタフエース、ＢＤ１，ＢＤ２，ＢＤ
３，ＢＤ４……レジスタ、ＣＳ１，ＣＳ２，ＣＳ
３，ＣＳ４……セレクト信号、ＡＤＢ……アドレ
スバス、ＤＥＣ……アドレスバスデコーダ、ＥＮ
……イネーブル、ＳＧ１，ＳＧ２，ＳＧ３，ＳＧ
４……設定スイツチ。
FIG. 1 is a diagram showing details of a priority value setting switch circuit of a control device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a connection configuration between the control device and input/output devices of the present invention. 1a, 1b, 1c, 1d...input/output device, 2...
...control device body, 2a, 2b, 2c, 2d...channel interface, BD1, BD2, BD
3, BD4...Register, CS1, CS2, CS
3, CS4...Select signal, ADB...Address bus, DEC...Address bus decoder, EN
...Enable, SG1, SG2, SG3, SG
4... Setting switch.
Claims (1)
各チヤンネルインタフエースに入出力装置を接続
し、マイクロプログラムによるサービスを行なう
データ処理装置入出力制御装置において、前記の
各チヤンネルインタフエースにプライオリテイ値
（優先度値）を設定するための設定スイツト回路
を設け、前記スイツチ回路に設定された割込み優
先度値を前記チヤンネルインタフエースより前記
マイクロプログラムに通知することを特徴とする
データ処理装置入出力制御装置。 In a data processing device input/output control device that has channel interfaces, connects input/output devices to these channel interfaces, and performs services based on microprograms, each channel interface has a priority value (priority level). 1. An input/output control device for a data processing device, characterized in that a setting switch circuit is provided for setting an interrupt priority value), and the interrupt priority value set in the switch circuit is notified to the microprogram from the channel interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP922085U JPS61128747U (en) | 1985-01-28 | 1985-01-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP922085U JPS61128747U (en) | 1985-01-28 | 1985-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128747U true JPS61128747U (en) | 1986-08-12 |
Family
ID=30489232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP922085U Pending JPS61128747U (en) | 1985-01-28 | 1985-01-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128747U (en) |
-
1985
- 1985-01-28 JP JP922085U patent/JPS61128747U/ja active Pending
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