JPS61125196A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPS61125196A JPS61125196A JP59247123A JP24712384A JPS61125196A JP S61125196 A JPS61125196 A JP S61125196A JP 59247123 A JP59247123 A JP 59247123A JP 24712384 A JP24712384 A JP 24712384A JP S61125196 A JPS61125196 A JP S61125196A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- signal
- ground
- polyimide
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は回路基板、特に、高速コ／ビエータにおけるよ
うに、高速なスイッチング動作を行なう集積回路を高密
度実装するのに好適な回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit board, and particularly to a circuit board suitable for high-density packaging of integrated circuits that perform high-speed switching operations, such as in high-speed co/viators. .
（従来の技術）
従来のこの種の回路基板の一例は、内層にそれぞれが一
層または複数の第１のグランド層と第１の電源層とを有
するセラミック基板の一方の面の全面ないしはほゞ全面
にコンタクトピンを、また他方の面にはこ几らコンタク
トピンと電気的に接続されたパッドをそれぞれ備え、パ
ッド層の上にポリイミドを介して少なくとも一つの信号
層が形成されている。(Prior Art) An example of a conventional circuit board of this type is a ceramic substrate that has one or more first ground layers and a first power supply layer in its inner layers, and has one surface or almost the entire surface of the ceramic substrate. A contact pin is provided on one side, and a pad electrically connected to the contact pin is provided on the other side, and at least one signal layer is formed on the pad layer via polyimide.
（発明が解決しようとする問題点）
このような従来構成においては、信号層はグランド層ま
ｔは電源層との間隔が大きいために、信号線の特性イン
ピーダンスが高く、信号線間のクロストーク雑音が大き
いという問題点がある。(Problems to be Solved by the Invention) In such a conventional configuration, since the signal layer has a large distance from the ground layer or the power supply layer, the characteristic impedance of the signal line is high and crosstalk between the signal lines occurs. The problem is that there is a lot of noise.
したがって、本発明の目的は、信号線間のクロストーク
雑音の低下を図っ几回路基板を提供することにある。Therefore, an object of the present invention is to provide a circuit board that reduces crosstalk noise between signal lines.
（問題点を解決するための手段）
そのｔめに、第１の本発明の回路基板は、内層にそれぞ
れが一つまたは複数の第１のグランド層と第１の電源層
とを有するセラミック基板の一方の面の全面ないしはは
ゾ全面にコンタクトビ／を、ま几他方の面には該コンタ
クトビ／と電気的に接続されたパッドをそれぞｎ備え、
該バンドの上にポリイミドを介して少なくとも一つの信
号層を、該信号層の最上層の上に前記ポリイミドを介し
て第３のグランドまたは電源層をそれぞれ形成し九こと
を特徴とする。(Means for Solving the Problems) To that end, the circuit board of the first invention includes a ceramic substrate each having one or more first ground layers and a first power layer in the inner layer. A contact pin is provided on the entire surface or the entire surface of one side, and a pad electrically connected to the contact pin is provided on the other side,
At least one signal layer is formed on the band via polyimide, and a third ground or power layer is formed on the top layer of the signal layer via the polyimide.
また、第２の本発明の回路基板は、内層にそれぞれが一
つまたは複数の第１のグランド層と第１の電源層とを有
するセラミック基板の一方の面の全面ないしははゾ全面
にコアタクトビアｔ−１また他方の面には該コンタクト
ピンと電気的に接続されたパッドをそれぞれ備え、該パ
ッドと同一層にメッシュ状の第２のグランドまたは電源
層を、該層の上にポリイミドを介して少なくとも一つの
信号層を、該信号層の最上層の上に前記ポリイミドを介
して第３のグランドまｔは電源層をそれぞれ形成したこ
とを特徴とする。Further, in the circuit board of the second aspect of the present invention, a core tact via t is provided on the entire surface or the entire surface of one surface of the ceramic substrate, each of which has one or more first ground layers and a first power layer in the inner layer. -1 The other side is provided with a pad electrically connected to the contact pin, and a mesh-like second ground or power layer is provided on the same layer as the pad, and at least The present invention is characterized in that one signal layer is provided, and a third ground or power layer is formed on the top layer of the signal layer via the polyimide.
（実施例）
第２の本発明の一実施例の断面図を示す第１図を参照す
ると、本実施例は、内層に第１のグランド層Ｇ１と第１
の電源層ＰＩとを有するセラミック基板ＣＢの下面全面
にコンタクトピンＣＰを、また上面全面にコンタクトピ
ンＣＰとはスルーホールＴＨｔ−介して電気的に接続さ
れたパッドＰＤをそれぞれ備え、パッドＰＤと同一層に
メツシュ状の第２の電源層Ｐ ２ ｔ” ｓこの第２の
電源層Ｐ２の上にポリイミドＰＩ′ｆ：絶縁層とする第
１の信号層Ｓｌと第２の信号層Ｓ２を、第２の信号層Ｓ
２の上にポリイミドＰＴｉ介して第２のグランド層Ｇ２
がそれぞれ形成されている。ポリイミドＰＩは高絶縁性
と低比誘電率とを有する良質の絶縁体であシ、この種の
回路基板によく採用される。(Embodiment) Referring to FIG. 1 showing a cross-sectional view of an embodiment of the second invention, this embodiment has a first ground layer G1 and a first ground layer G1 in the inner layer.
A ceramic substrate CB having a power supply layer PI has a contact pin CP on the entire bottom surface, and a pad PD electrically connected to the contact pin CP through a through hole THt on the entire top surface. A mesh-like second power supply layer P 2 t''s is formed on the second power supply layer P2, and a first signal layer Sl and a second signal layer S2, each made of polyimide PI'f as an insulating layer, are formed on the second power supply layer P2. 2 signal layer S
A second ground layer G2 is formed on top of G2 via polyimide PTi.
are formed respectively. Polyimide PI is a high-quality insulator with high insulation properties and low dielectric constant, and is often used in this type of circuit board.
図示を省略するが、集積回路チップが第２のグランド層
Ｇ２の上に実装され、第１の信号層８１゜第２の信号層
８２．第１の電源層ＰＩ、第２の電源層Ｐ２．第１のグ
ランド層Ｇ１および第２のグランド層Ｇ２とスルーホー
ルを介して接続される。Although not shown, an integrated circuit chip is mounted on the second ground layer G2, with the first signal layer 81, the second signal layer 82, and so on. First power layer PI, second power layer P2. It is connected to the first ground layer G1 and the second ground layer G2 via through holes.
第１図から明らかなように、セラミック基板ＣＢとポリ
イミドＰＩＯ間には第２の電源層Ｐ２が介在するために
、両者は電磁的に遮へいされる。As is clear from FIG. 1, since the second power supply layer P2 is interposed between the ceramic substrate CB and the polyimide PIO, both are electromagnetically shielded.
し友がって、第１の信号層Ｓ１および第２の信号層Ｓ２
における実効比誘電率εｒ０は、ポリイミドの比誘電率
には望等しくなる。第１の信号層Ｓ１および第２の信号
層Ｓ２における信号の伝搬遅延時間Ｔ（ｎｓ／ｍ）は、
一般に、次式で表わされるために、
Ｔ＝３．３３５６−
伝搬遅延時間Ｔは、実効誘電率ε、。の低下につれて小
さくなることがわかる。Accordingly, the first signal layer S1 and the second signal layer S2
The effective dielectric constant εr0 at is desirably equal to the dielectric constant of polyimide. The signal propagation delay time T (ns/m) in the first signal layer S1 and the second signal layer S2 is
Generally, since it is expressed by the following equation, T = 3.3356 - the propagation delay time T is the effective dielectric constant ε,. It can be seen that the value decreases as the value decreases.
ま友、第１の信号層Ｓ１および第２の信号層Ｓ２は、そ
の上下が第２のグランド層Ｇ２と第２の電源層Ｐ２とで
覆われる九めに、第１の信号層８１および第２の信号層
Ｓ２とグランド層または電源層との間隔が小さくなり、
特性インピーダンスは低下し、信号線間のクロストーク
雑音が低下する。The first signal layer S1 and the second signal layer S2 are covered with the second ground layer G2 and the second power layer P2 on the top and bottom, and the first signal layer 81 and the second signal layer S2 are covered with the second ground layer G2 and the second power layer P2. The distance between the signal layer S2 of No. 2 and the ground layer or power layer becomes smaller,
Characteristic impedance is lowered, and crosstalk noise between signal lines is reduced.
第１の本発明の一実施例は、第１図において、第２の電
源層Ｐ２を除去し九図によって容易に示すことができる
。An embodiment of the first invention can be easily illustrated in FIG. 9 by removing the second power supply layer P2 from FIG.
この場合にも、第２のグランド層Ｇ２の存在のｔめに、
第１の信号層Ｓ１および第２の信号層Ｓ２とグランド層
との間隔が小さくなり、特性インピーダンスは低下し、
信号線間のクロストーク雑音が低下する。Also in this case, due to the existence of the second ground layer G2,
The distance between the first signal layer S1 and the second signal layer S2 and the ground layer becomes smaller, the characteristic impedance decreases,
Crosstalk noise between signal lines is reduced.
しかしながら、セラミック基板ＣＢとボリイミドＰＩと
を電磁的に遮へいするものが無いために、第１の信号層
８１および第２の信号層Ｓ２における信号の伝搬遅延時
間は、従来とほとんど同程度の１工である。However, since there is nothing to electromagnetically shield the ceramic substrate CB and the polyimide PI, the signal propagation delay time in the first signal layer 81 and the second signal layer S2 is almost the same as in the conventional case. It is.
以上に述べたすべての実施例においては、第１の電源層
ＰＩおよび第１のグランド層Ｇ１は、それぞれ一層であ
るが、これらは複数層であってもよい。In all the embodiments described above, the first power supply layer PI and the first ground layer G1 each have a single layer, but they may have multiple layers.
ｔｔ１第２の電源層Ｐ２と第２のグランド層Ｇ２とが入
れ替ってもよいし、両方の層とも電源層あるいはグラン
ド層であってもよい。tt1 The second power layer P2 and the second ground layer G2 may be exchanged, or both layers may be a power layer or a ground layer.
（発明の効果）
本発明によれば、以上のような構成の採用によって、信
号線間のりａストーク雑音を低下させ、高速スイッチン
グ動作を行なう集積回路を高密度に実装するのに好適な
回路基板を得ることができるようになる。(Effects of the Invention) According to the present invention, by employing the above-described configuration, a stalk noise between signal lines can be reduced, and a circuit board suitable for densely mounting integrated circuits that perform high-speed switching operations can be obtained. You will be able to obtain
第１図は第２の本発明の一実施例を示す。
ＣＢ・・・・・・セラミック基板、ＰＩ・・・・・・ポ
リイミド、ＣＰ・・・・・・コンタクトビ／、ＰＤ・・
・・・・パッド、ＰＩ・・・・・・第１の電源層、Ｐ２
・・・・・・第２の電源層、Ｇｌ・・・・・・第１のグ
ランド層、Ｇ２・・・・・・第２のグランド層、８１・
・・・・・第１の信号層、Ｓ２・°“・・・第２の信号
層。FIG. 1 shows an embodiment of the second invention. CB... Ceramic substrate, PI... Polyimide, CP... Contact Bi/, PD...
...Pad, PI...First power layer, P2
...Second power supply layer, Gl...First ground layer, G2...Second ground layer, 81.
...First signal layer, S2.°" ...Second signal layer.
Claims (2)
ド層と第１の電源層とを有するセラミック基板の一方の
面の全面ないしはほゞ全面にコンタクトピンを、また他
方の面には該コンタクトピンと電気的に接続されたパッ
ドをそれぞれ備え、該パッドの上にポリイミドを介して
少なくとも一つの信号層を、該信号層の最上層の上に前
記ポリイミドを介して第３のグランドまたは電源層をそ
れぞれ形成したことを特徴とする回路基板。(1) Contact pins are provided on the entire surface or almost the entire surface of one surface of a ceramic substrate, each of which has one or more first ground layers and a first power source layer on the inner layer, and contact pins are provided on the other surface. Each pad is electrically connected to a contact pin, and at least one signal layer is provided on the pad via polyimide, and a third ground or power layer is provided on the top layer of the signal layer via the polyimide. A circuit board characterized in that each of these is formed.
ド層と第１の電源層とを有するセラミック基板の一方の
面の全面ないしはほゞ全面にコンタクトピンを、また他
方の面には該コンタクトピンと電気的に接続されたパッ
ドをそれぞれ備え、該パッドと同一層にメッシュ状の第
２のグランドまたは電源層を、該層の上にポリイミドを
介して少なくとも一つの信号層を、該信号層の最上層の
上に前記ポリイミドを介して第３のグランドまたは電源
層をそれぞれ形成したことを特徴とする回路基板。(2) Contact pins are provided on the entire surface or almost the entire surface of one surface of a ceramic substrate, each of which has one or more first ground layers and a first power supply layer on the inner layer, and contact pins are provided on the other surface. Each pad is electrically connected to the contact pin, a mesh-like second ground or power layer is provided on the same layer as the pad, and at least one signal layer is provided on the layer through polyimide, the signal layer. A circuit board characterized in that a third ground layer or a power source layer is formed on the uppermost layer of the substrate via the polyimide.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247123A JPS61125196A (en) | 1984-11-22 | 1984-11-22 | Circuit board |
| US06/724,587 US4754371A (en) | 1984-04-27 | 1985-04-18 | Large scale integrated circuit package |
| FR8506423A FR2563656B1 (en) | 1984-04-27 | 1985-04-26 | LARGE-SCALE INTEGRATION CIRCUIT BLOCK |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247123A JPS61125196A (en) | 1984-11-22 | 1984-11-22 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61125196A true JPS61125196A (en) | 1986-06-12 |
| JPH0353795B2 JPH0353795B2 (en) | 1991-08-16 |
Family
ID=17158771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59247123A Granted JPS61125196A (en) | 1984-04-27 | 1984-11-22 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125196A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01262696A (en) * | 1988-03-11 | 1989-10-19 | Internatl Business Mach Corp <Ibm> | Electronic circuit board structure |
| JPH08293649A (en) * | 1995-04-21 | 1996-11-05 | Tinchiichiie Yugenkoshi | Low crosstalk signal transmission medium |
-
1984
- 1984-11-22 JP JP59247123A patent/JPS61125196A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01262696A (en) * | 1988-03-11 | 1989-10-19 | Internatl Business Mach Corp <Ibm> | Electronic circuit board structure |
| JPH08293649A (en) * | 1995-04-21 | 1996-11-05 | Tinchiichiie Yugenkoshi | Low crosstalk signal transmission medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0353795B2 (en) | 1991-08-16 |
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