JPS61125132A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61125132A
JPS61125132A JP59247114A JP24711484A JPS61125132A JP S61125132 A JPS61125132 A JP S61125132A JP 59247114 A JP59247114 A JP 59247114A JP 24711484 A JP24711484 A JP 24711484A JP S61125132 A JPS61125132 A JP S61125132A
Authority
JP
Japan
Prior art keywords
pattern
positioning
alignment
photomask
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59247114A
Other languages
Japanese (ja)
Inventor
Hisashi Haneda
尚志 羽田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59247114A priority Critical patent/JPS61125132A/en
Publication of JPS61125132A publication Critical patent/JPS61125132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To remove variation of positioning accuracy by a method wherein positioning is performed using a positioning template of a photomask containing a bisector of a polygonal angle or parallel line thereof of the positioning pattern in a photo-lithography process. CONSTITUTION:A pattern 1 is a positioning pattern on the surface of a substrate, while a broken-lined pattern 5 is a one being enlarged proportionally on a surface of a semiconductor, and a broken-line pattern 6 is a one being reduced proportionally on the surface of the semiconductor. At the positioning pattern (b) of a photomask, two rectangles 3, which contain bisectors of regular square angles and parallel straight line of the pattern 1 with margin of positioning are disposed and they are provided to each angle sections. For positioning the pattern (b) and (a), the regular square angle corners of the pattern 1 are set between the margins 4 of positioning. At this time, even if the regular square 1 is enlarged to the shape of the broken-line 5 at previous process or is reduced to the broken-line 6, the angle corners can be taken in the margin of positioning 4, thereby the accuracy of positioning does not change.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に7オ) I
Jソゲラフイエ程を改良した半導体装置の製造方法に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, 7) I)
This invention relates to a method for manufacturing a semiconductor device that is an improvement on the J. Sogerahuie process.

〔従来の技術〕[Conventional technology]

従来、フォトリングラフィ工程では半導体基板表面に既
に加工されたパターンとの整合をとるため、目合せパタ
ーンによりフォトマスクと半導体基板表面との位置関係
を一致させているが、従来の方法は半導体基板表面にあ
らかじめパターンを形成しておき、そのパターンの直線
と、フォトマスクのパターンの直線との位置関係で目合
せを行っていた。第4図fat 、 (b) 、 tc
+は従来の目合せパターン及びその目合せ方法を説明す
るための図である。半導体基板表面に基板段差、基板上
の被膜段差もしくは被膜の有無等によって第4図(al
のようなパターンを形成し、フォトマスクには例えば第
4図(blのように半導体基板表面に形成した正方形の
パターンよりわずかに小さな正方形のパターンを設け、
基板表面の正方形パターンの内側にフォトマスクの正方
形パターンをはめ込んで第4図(C1に示すように配置
することで基板とフォトマスクの整合をとっている。こ
こで通常目金せ精度の点から1の各辺の寸法と第4図(
blに示す正方形2の各辺の寸法とに差をもたせ、正方
形1の内部に正方形2が入っていれば問題はなく、はみ
出せば不良となるように設計されている。
Conventionally, in the photolithography process, alignment patterns are used to match the positional relationship between the photomask and the semiconductor substrate surface in order to match the pattern already processed on the semiconductor substrate surface. A pattern was previously formed on the surface, and alignment was performed based on the positional relationship between the straight lines of the pattern and the straight lines of the photomask pattern. Figure 4 fat, (b), tc
+ is a diagram for explaining a conventional alignment pattern and its alignment method. Figure 4 (al.
For example, a square pattern slightly smaller than the square pattern formed on the surface of the semiconductor substrate is provided on the photomask, as shown in FIG.
The substrate and photomask are aligned by fitting the square pattern of the photomask inside the square pattern on the substrate surface and arranging them as shown in Figure 4 (C1). The dimensions of each side of 1 and Figure 4 (
It is designed so that the dimensions of each side of the square 2 shown in bl are different, and if the square 2 is inside the square 1, there is no problem, but if it protrudes, it is a defect.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、工程によっては既に形成した半導体基板
表面の第4図[alに示すパターンが比例拡大もしくは
縮小する場合があり、拡大されていれば第4図1a)の
パターン1に第4図(blのパターン2がはみ出さずに
入っていても不良になる場合があり、又縮小されていれ
ば、第4図(alのパターン1に第4図(blのパター
ン2を入れることが出来ない場合があυ得るという欠点
があった。
However, depending on the process, the pattern shown in FIG. 4 [al] on the surface of the semiconductor substrate that has already been formed may be proportionally enlarged or reduced, and if it is enlarged, pattern 1 in FIG. Even if pattern 2 is included without protruding, it may be defective, and if it is reduced, it may not be possible to insert pattern 2 in figure 4 (bl) into pattern 1 in figure 4 (al). It had the disadvantage of getting a nuisance.

本発明はかかる欠点を除去し、半導体基板表面に形成さ
れた目合せパターンが比例拡大、もしくは縮小するよう
な工程を有する半導体装置の製造方法におけるフォトリ
ソグラフィ工程においても目合せ精度に変化のないリソ
グラフィ工程を有する半導体装置の製造方法を提供する
ことを目的とする。
The present invention eliminates such drawbacks and provides lithography that does not change the alignment accuracy even in the photolithography process of a semiconductor device manufacturing method, which has a process in which an alignment pattern formed on the surface of a semiconductor substrate is proportionally enlarged or reduced. An object of the present invention is to provide a method for manufacturing a semiconductor device that includes steps.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、半導体基板主面を加
工するフォ) IJソゲラフイエ程において、前記半導
体基板主面に基板の段差、基板上の被膜の段差もしくは
被膜の有無による直線で形成された多角形の角部を有す
るパターンに対し、露光で使用するフォトマスクとの目
合せのための目合せパターンを前記多角形の角部な有す
るパターンの角部の二等分線もしくはその平行線を有す
る形状に形成し、両パターンを目合せすることによシ構
成される。
In the method for manufacturing a semiconductor device of the present invention, in the IJ sogerafye step of processing the main surface of the semiconductor substrate, steps of the semiconductor substrate, steps of the film on the substrate, or straight lines formed due to the presence or absence of the film are formed on the main surface of the semiconductor substrate. For a pattern having polygonal corners, an alignment pattern for alignment with a photomask used in exposure is made by using a bisector of the corner of the polygonal corner or a parallel line thereof. It is constructed by forming the pattern into a shape having the same shape and aligning both patterns.

〔実施例〕〔Example〕

以下、本発明の実施例について、図面を参照して説明す
る。第1図は本発明の第1の実施例を説明するための目
合せパターン及び目合せ方法を説明するための図である
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining an alignment pattern and an alignment method for explaining a first embodiment of the present invention.

第1図1a)において、実線で表示し九パターン1は従
来例で記した第2図1alと同様のパターンであシ、破
線で示したパターン5は比例拡大した半導体基板表面の
目合せパターン、又、パターン6は比例縮小した半導体
基板表面の目合せパターンである。
In FIG. 1 1a), pattern 1 indicated by a solid line is the same pattern as FIG. Further, pattern 6 is an alignment pattern on the surface of the semiconductor substrate which is proportionally reduced.

第1図(blは本発明に使用するフォトマスクの目合せ
パターンで第1図(alのパターン1の正方形の角部の
二等分線に平行な直線を含む長方形3を目合せ余裕4を
もたせて2個配置したものを各角部に設けたものである
Figure 1 (bl is the alignment pattern of the photomask used in the present invention. Figure 1 (al) is a rectangle 3 that includes a straight line parallel to the bisector of the corner of the square in pattern 1, and alignment margin 4 is Two pieces are placed side by side at each corner.

M l 図(blのパターンと第2図1alのパターン
ヲ目合せするには第1図(C1に示すように目合せ余裕
40間にパターン1の正方形の角部を合わせる。この時
1の正方形が前工程で拡大し5の破線のようになった場
合でも、縮小して6の破線のようになった場合でも目合
せ余裕4の中に角部を入れることができ、目合せ精度も
変らない。
To align the pattern in Figure Ml (bl) and the pattern in Figure 2 1al, align the corner of the square of pattern 1 with an alignment margin of 40 as shown in Figure 1 (C1).At this time, the square of pattern 1 Even if it is enlarged in the previous process and becomes like the broken line in 5, or if it is reduced and becomes like the broken line in 6, the corner can be placed within the alignment margin of 4, and alignment accuracy will not change. .

第2図1al 、 (b)は本発明の第2の実施例を説
明するためのマスク目合せパターン及び目合せ方法を説
明するための図である。第2図1alのマスク目合せパ
ターン7はパターン1の正方形の角部の二等分線に平行
な直線を含む三角形状に形成され角部の二等分線に対し
対照的に配置されている。この場合も第2図(b)に示
すように重ね合わせることにJ−シ第1の実施例と同様
の効果が得られる。
FIGS. 2A and 2B are diagrams for explaining a mask alignment pattern and an alignment method for explaining a second embodiment of the present invention. The mask alignment pattern 7 in FIG. 2 1al is formed in a triangular shape including a straight line parallel to the bisector of the corner of the square of pattern 1, and is arranged in contrast to the bisector of the corner. . In this case as well, the same effect as in the first embodiment of J-C can be obtained by overlapping them as shown in FIG. 2(b).

第3図(al 、 (bl 、 (C1は本発明の第3
の実施例を説明するための半導体基板表面の目合せパタ
ーン、フォトマスクの目合せパターン及び目合せ方法を
説明するための図である。
FIG. 3 (al, (bl, (C1 is the third embodiment of the present invention)
FIG. 2 is a diagram for explaining an alignment pattern on the surface of a semiconductor substrate, an alignment pattern of a photomask, and an alignment method for explaining an embodiment of the present invention.

第2図1al 、 (b) 、 (C)において、8は
半導体基板上の目合せパターン、9は比例拡大した半導
体基板表面の目合せパターン、10は比例縮小した半導
体基板表面の目合せパターン、また11はフォトマスク
の目合せパターンである。この場合もフォトマスクの目
合せパターン11はパターン8の正方形の角部の二等分
線に平行な直線を含み平方形に形成されており、第3図
(C1の様に重ねることにより前記した実施例と同様の
効果がある。
In FIG. 2 1al, (b) and (C), 8 is an alignment pattern on the semiconductor substrate, 9 is an alignment pattern on the semiconductor substrate surface proportionally enlarged, 10 is an alignment pattern on the semiconductor substrate surface proportionally reduced, Further, 11 is an alignment pattern of the photomask. In this case as well, the alignment pattern 11 of the photomask is formed into a square shape including a straight line parallel to the bisector of the corner of the square of the pattern 8. There are effects similar to those of the embodiment.

なお上記実施例においてはフォトマスクの目合せパター
ンは半導体基板表面の目合せパターンの角部の二等分線
に平行な直線を含んで構成された例について述べたが、
中心線としてもよく、また目合せ余裕をとるためには巾
を持った中心線、枠取シされた中心線を含む矩形パター
ンでもよい。
In the above embodiment, an example was described in which the alignment pattern of the photomask included a straight line parallel to the bisector of the corner of the alignment pattern on the surface of the semiconductor substrate.
It may be a center line, or it may be a rectangular pattern including a center line with width or a center line with a frame in order to provide alignment margin.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、半導体基板に形
成され九目金せパターンが比例拡大もしくは縮小するよ
うな工程を有する半導体装置の製造方法におけるフォト
リングラフィ工程において、その目合せパターンの多角
形の角部の二等分線もしくはその平行線を含むフォトマ
スクの目合せパターンを用いて、目合せすることによ)
目合せ精度に変化の無いりソゲラフイエ程を得ることが
できる。
As explained above, according to the present invention, in the photolithography process of a semiconductor device manufacturing method that includes a process in which a nine-metal alignment pattern formed on a semiconductor substrate is proportionally enlarged or reduced, the alignment pattern is (By aligning using a photomask alignment pattern that includes the bisector of the corner of the polygon or its parallel lines)
There is no change in alignment accuracy, and it is possible to obtain a level of alignment accuracy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図Tal 〜(C1、第2図(al 、 (bl、
第3図(aJ〜fclは何れも本発明の詳細な説明する
ための半導体基板表面の目合せパターン、フォトマスク
の目合せパターン及び目合せ方法を説明するための説明
図、第4図[al〜(C1は従来方法を説明するだめの
半導体基板の目合せパターン、フォトマスク目金せパタ
ーン及び目合せ方法を説明するための説明図である。 1、訃・・・・・半導体基板表面の目合せパターン、&
3.7.11・・・・・・フォトマスクの目合せパター
ン、4・・・・・・目合せ余裕、5.9・・・・・・比
例拡大した半導体基板表面の目合せパターン、6.10
・・・・・・比例縮小した半導体基板表面の目合せパタ
ーン。 代理人 弁理士  内 原   晋 〜パ’:”’+、
+ 竿/ 回 (al (b) 第 2fJ (刹 稟3 図 (αン (よン (C> 第4圀
Figure 1 Tal ~ (C1, Figure 2 (al, (bl,
FIG. 3 (aJ to fcl are explanatory diagrams for explaining the alignment pattern on the surface of the semiconductor substrate, the alignment pattern of the photomask, and the alignment method for explaining the present invention in detail, and FIG. 4 [al ~ (C1 is an explanatory diagram for explaining the alignment pattern of the semiconductor substrate, the photomask alignment pattern, and the alignment method, which is not used to explain the conventional method. 1. The pattern of the semiconductor substrate surface alignment pattern, &
3.7.11... Alignment pattern of photomask, 4... Alignment margin, 5.9... Alignment pattern of proportionally enlarged semiconductor substrate surface, 6 .10
.....Alignment pattern on the surface of a semiconductor substrate proportionally reduced. Agent Patent Attorney Susumu Uchihara 〜Pa':”'+、
+ rod / times (al (b) 2nd fJ (刹稟3 fig.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板主面を加工するフォトリソグラフィ工程に
おいて、前記半導体基板主面に基板の段差、基板上の被
膜の段差もしくは被膜の有無による直線で形成された多
角形の角部を有するパターンに対し、露光で使用するフ
ォトマスクとの目合せのための目合せパターンを前記多
角形の角部を有するパターンの角部の二等分線もしくは
その平行線を有する形状に形成し、両パターンを目合せ
することを特徴とする半導体装置の製造方法。
In a photolithography process for processing the main surface of a semiconductor substrate, a pattern having polygonal corners formed by steps of the substrate, steps of a film on the substrate, or straight lines due to the presence or absence of a film on the main surface of the semiconductor substrate is exposed to light. An alignment pattern for alignment with a photomask used in the process is formed in a shape having a bisector of the corner of the pattern having polygonal corners or a parallel line thereof, and both patterns are aligned. A method for manufacturing a semiconductor device, characterized in that:
JP59247114A 1984-11-22 1984-11-22 Manufacture of semiconductor device Pending JPS61125132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59247114A JPS61125132A (en) 1984-11-22 1984-11-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59247114A JPS61125132A (en) 1984-11-22 1984-11-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61125132A true JPS61125132A (en) 1986-06-12

Family

ID=17158641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59247114A Pending JPS61125132A (en) 1984-11-22 1984-11-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61125132A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821687B2 (en) 2001-04-02 2004-11-23 Nec Electronics Corporation Photo mask for fabricating semiconductor device having dual damascene structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821687B2 (en) 2001-04-02 2004-11-23 Nec Electronics Corporation Photo mask for fabricating semiconductor device having dual damascene structure

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