JPS61123979A - Real time animation processor - Google Patents

Abstract

PURPOSE:To apply an animation signal to seal time processing by sequentially connecting to plural delayed circuits where the amount of delay is increased by one unit each. CONSTITUTION:From synchronous signals notifying start of a picture frame of TV signal such as an animation signal, a control part 13 generates a prescribed input sectional screen positioning signal and an output sectional screen positioning signal. A taking in part 10 inputs the input sectional screen positioning signal from the control part 13, and separately takes in sectional screen signal designated by the input sectional screen positioning signal of the inputted animation signal. The processed results accumulated in the said designated section screen position from the control part 13 are outputted from the output part, constituting a unit processor. By providing input means for one unit processor for every delayed circuit, such delayed circuit being plural for delaying each sample by every sample timing of synchronous signal and animation signal and via a delayed circuit which delays the synchronous signal and animation signal. Thereby a real time animation processor is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a real-time signal processing processor that implements digital signal processing such as digital filtering and high-efficiency signal processing for video signals such as television signals using software. .

(Toramai technology and its problems) The advantage of real-time digital signal processing is that it is possible to create filters and modulation/demodulators with guaranteed high precision or high stability, which cannot be achieved with analog technology, and it is also unimaginable with analog signal processing. For example, time-varying adaptive filters and the like can be easily realized. Furthermore, by incorporating the results of digital LSI technology, which has developed rapidly in recent years, it has become possible to make real-time digital signal processing circuits smaller and lower power consumption, and they are gradually being used to replace analog circuits and improve functionality. It is progressing towards. For more detailed information on the advantages of digital signal processing, please refer to pages 1280 to 1284 of the December 1982 issue of the Journal of the Institute of Electronics and Communication Engineers.

Although digital signal processing has many advantages, it also has the disadvantage of requiring a large amount of calculation. To perform real-time signal processing, it is necessary to perform the given digital signal processing within the sampling period for each sample of the input signal. For example, for telephone voice (8kHz sampling), When performing cyclic digital filter processing, eight multiplications and eight additions are required within 125 microseconds.

Therefore, in order to perform signal processing on a video signal whose frequency bandwidth is more than 1,000 times wider than that of telephone audio, and the sampling period is also less than 171,000, a circuit that is more than 1,000 times faster than a signal processing circuit for telephone audio is required. It becomes necessary. For this reason, advanced digital signal processing can currently only be performed on signals in the audio domain, and video signal processing is currently limited to extremely simple processing.

Furthermore, regarding digital signal processing for signals in the audio domain, we want to perform high-speed digital signal processing.
Often, various parameters are changed or part of the signal processing algorithm is changed. Therefore, there is a strong demand for a signal processing device whose algorithms and parameters can be changed using software. Conventional hardware that performs digital signal processing using software is the IEEE Journal of Solid State Circuits (IEEE Journal of Solid State Circuits).
There is a signal processor published on pages 372 to 376 of Volume 5C-16, No. 4 (August 1981), and a typical application example of this signal processor is Proceedings Op International Conference On Acoustakes Speech Signal 32kbp published on page 963 from Procera
s ADPCM, which is also aimed at telephone voice processing.

With conventional processors like this, no matter how much you speed up the arithmetic circuit, it is not easy to achieve a speed increase of more than 1000 times, so it is not suitable for software-controlled processors that perform advanced digital signal processing on video. there were.

(Object of the Invention) An object of the present invention is to provide a software-controlled circuit that can perform advanced digital signal processing on video signals such as television signals.

Another object of the present invention is to provide a method of adding processors without impairing the signal transmission capability of the hardware when connecting a large number of processors when signal processing is performed on a video signal by multiple processors. be.

(Structure of the Invention) According to the present invention, the control section generates a predetermined input partial screen position signal and output partial screen position signal based on a synchronization signal that indicates the start of one screen of a moving image signal such as a television signal; The input partial screen position signal is input from the control unit,
a capture unit that captures a partial screen signal specified by the input partial screen position signal of a separately input video signal; It is connected to a processing unit that performs signal processing before screen capture starts, and to the output side of the processing unit, and stores the processing results of the processing unit, and also stores the output partial screen position signal input from the control unit. a plurality of unit processors comprising an output section that outputs the stored processing results at a specified partial screen position; and a plurality of unit processors that delay the synchronization signal and the video signal by one sample at each sample time. a delay circuit; means for inputting the synchronization signal delayed through the delay circuit and the video signal to one unit processor for each delay circuit; and a connection to each of the plurality of delay circuits. means for delaying the outputs of the plurality of unit processors in order of decreasing amount of delay by the delay circuit, and combining the outputs of the plurality of unit processors with the amount of delay by one more by the delay circuit; The output partial screens predetermined by the unit processors are processed so that there is no overlap between the unit processors, and the predetermined input partial screen signals are processed so as to allow overlap, and the input/output signals of each unit processor are processed in a pipeline. A real-time video processor is obtained which is characterized in that it is connected.

(Principle of the Invention) The principle of the present invention is to divide one screen (frame) into multiple partial screens, assign one unit signal processor to each partial screen, and pipeline the input/output signals of each unit processor. The purpose of this is to make it possible to add unit processors without impairing the signal transmission ability of the hardware even if unit processors are connected in multiple stages. First, if a video is treated as a one-dimensional signal suitable for signal transmission, it needs to be sampled at about 10 MHz, as mentioned above, and in this case, it is necessary to process each sample within a period of 100 psee. However, if a video signal is treated as a two-dimensional signal called a screen, for example, a television signal only sends 30 screens per second. That is 33
If one screen can be processed in milliseconds, there will be a delay of one screen, but real-time performance will be maintained.

In order to process this sampled signal for one screen, multiple unit processors are prepared, and the area to be processed is set in advance between each unit signal processor, and each unit signal processor is assigned a partial screen area to be processed. To selectively capture video signals necessary for

In this case, the capture partial screen is generally larger than the processing partial screen.

For example, a two-dimensional sampled signal at coordinates (i, j) is expressed as x(i, j
) and this two-dimensional signal t impulse response (h(i
, j)). Here the output (
i, j) are respectively subscreens 0. It is assumed that the impulse response h(i,j) belongs to the edge section P.

The filter operation at this time follows the following formula.

Therefore, the input signal (x(i
, j)), the interval Q of Q=((
Lj) knee (M+N)≦i≦face N1. −(M+N)≦j
≦(M ten groups) (3). Figure 2 shows data import screen Q
This shows the relationship between and the processing screen O.
A square captured image section Q of N) and a square processed image section 0 of side 2N are shown.

Equation (2) is called a convolution operation, but in addition to this, a correlation operation can also be expressed almost in the same way as Equation (2), and the relationship between the captured image and the processed image can be expressed as shown in FIG. As described above, although the regions of the captured image and the processed image are different in compo-union and correlation calculation, which are basic calculations in digital signal processing, if the region of the processed image is fixed, information on the entire screen is not necessary. Therefore, by dividing one @ screen into multiple partial screens and assigning multiple unit signal processors to process each partial screen, each unit signal processor can process the signal by capturing the signals for the required partial screen. can be performed independently in each unit signal processor. In other words, each unit signal processor only needs to process the assigned partial screen within 33 milliseconds, which is the sample period of one frame mentioned above, and by operating many unit signal processors in parallel, real-time video processing becomes possible.

When processing a screen using many unit signal processors like this, considering that all unit signal processors are arranged in parallel and image input and image output are connected through a common bus, data is transferred via these common buses. In order to do this, it is necessary to sufficiently increase the signal driving ability of the data sending section, which naturally places restrictions on the number of unit signal processors that can be connected. In order to eliminate this restriction, the input image signal and synchronization signal are delayed by one sample time using multiple delay circuits, and each unit signal processor is configured to receive an input signal given a different delay by each delay circuit. For example, since the transmitted signal is regenerated and relayed, the signal driving capacity may also be small. In this way, the output video signal will also be delayed by the amount of delay added to the input signal, so in order to combine the outputs of each unit signal processor, start from the output of the unit signal processor whose input signal has the least amount of delay.
It is sufficient to delay the sample time one by one and combine it with the output of the unit signal processor whose delay amount is equal.

(Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention in which four unit signal processors are used. Synchronous signal input terminals 1. Video signal input terminal 2. Unit signal processors 3, 4, 5, 6. Synchronous signal output terminal7. Video signal output terminal 8. Delay circuit 81.82
, 83, 91, 92, 93, and the unit signal processors 3, 4, 5.6 each have an input section 10. Processing unit 11. It consists of a reading section 12 and a control section 13. Intake part 10. The readout section 12 is a storage circuit, and the storage circuit of the readout section 12 has a tristate output (which can be in a high impedance state as an output). Processing section 11 and control section 13
The details will be described later. Delay circuits 81, 82, and 83 are registers made up of D-type flip-flops that transfer input data to output at each sampling time, and are each composed of two sets of registers, one for control signals and one for moving image signals. Furthermore, delay circuit 9
1.92,93. has a tristate output. This is a register consisting of a D-type flip-flop.

A synchronizing signal inputted from the terminal 1 is inputted to the control section 13 of the unit signal processor 3 and also inputted to the delay circuit 81. The control unit 13 built in the unit signal processor 3 identifies the point in time when a signal belonging to a pre-allocated capture partial screen area is input to the terminal 2 based on the input synchronization signal, and outputs the signal to the capture unit 10 as a capture signal. Notify.

The capture unit 10 captures and stores the moving image signal input to the terminal 2 based on the capture signal transmitted from the control unit 13.

The control unit 13 also transmits an execution signal to the processing unit 11 when the signal of a predetermined capture partial screen area has been input based on the synchronization signal input from the terminal 1.
Predetermined digital signal processing, for example, the convolution calculation of the above-mentioned formula (2), is performed on the captured video signal stored in the capture unit 10 using the execution signal input from the capture unit 10, and the result of the computation is sent to the readout unit 12. Write.

The control unit 13 further detects a predetermined processing partial screen area output time based on the synchronization signal input from the terminal 1, and when the processing partial screen area is reached, transmits an output command signal to the output unit 12. The processed data processed and written by the processing section 11 described above is sequentially output based on an output command signal from the processing section 13.

The synchronization signal applied to the terminal 1 and the video signal applied to the terminal 2 are transmitted to the control section 13 and the acquisition section 10 of the unit signal processor 4 after a delay of one sample time by the delay circuit 1. 4 internal control unit 1
3. Intake part 10. The processing section 11 and the output section 12 perform operations similar to those described above that occur inside the unit signal processor 3 on different partial screens.

Processors 5 and 6 also receive synchronization signals and video signals delayed by two and three sample times, respectively, through delay circuits 82 and 83, respectively, and perform the same processing as unit signal processors 3 and 4, respectively.

The output from the output unit 12 of the unit signal processor 3 is delayed by one sample time by the delay circuit 91. Since the delay circuit 91 is tri-stated only when the unit signal processor 4 outputs, the output of the unit signal processor 3 that has received a delay is also sent to the delay circuit 81.
If the synchronization signal that has been delayed is used as a reference, it will come to the correct screen position assigned to the unit signal processor 3.

For this reason, the output of the unit signal processor 3 delayed by the delay circuit 91 will not receive the synchronization signal appearing in the delay circuit 81 until the end of the period.
will be communicated to. When all the outputs of the unit signal processor 3 delayed by the delay circuit 91 have been transmitted to the delay circuit 92, the output command signal from the control section 13 of the unit signal processor 4 tristates the delay circuit 91 and outputs the output section 12.
Start supplying data from. Therefore, the delay circuit 92
Then, as soon as the output from the unit signal processor 3 via the delay circuit 91 is completed, the unit signal processor 4
The output will be taken as the delayed input. The output relationship between the unit signal processor 5 and the delay circuit 92 with respect to the synchronization signal from the delay circuit 81 is the same as the output relationship between the unit signal processor 4 and the delay circuit 91 with respect to the synchronization signal from the delay circuit 82. The relationship between the output of the circuit 92 and the synchronizing signal from the delay circuit 83 is also similar, so a description thereof will be omitted.

Figure 3 (a) to (d), (a') to (e')
, (f) and (g) are the acquired signals used in the unit signal processors 3 and 4 when the configuration shown in FIG. 1 is adopted;
This shows an execution signal and an output command signal. To simplify the explanation, the moving image signal used in FIG. 3 is assumed to have undergone scanning line conversion in which a normal scan signal covering the entire screen is rearranged for each partial screen. The synchronization signal (a) applied to the terminal 1 notifies the start of one screen, and in the unit signal processor 3 that processes the first divided screen, the acquisition signal (b) generated by the control section 13 is the synchronization signal. At the same time, it rises and continues commanding capture until the capture area ends. Furthermore, after the capture is completed, the control unit 13 transmits an execution signal (c) to the processing unit 11. The result processing unit 11 performs signal processing from the rise of the execution signal (c) to the next rise of the acquisition signal (b). The control section 13 also transmits an output command signal (d) to the output section 12. This output command signal can also be considered as a position signal of the processing partial screen of the unit signal processor 3. As explained in Fig. 2, the captured partial screen is generally larger than the processed partial screen, so the time when the signal (b) is on is longer than the signal (b) and (d) corresponding to each. (d) longer.

The signal (a') represents a synchronization signal delayed through the delay circuit 81. The signals (b'), (c'), and (d') are input signals of the unit processor 4 that processes the second partition screen. execution signal,
This is an output command signal. The relationship between the signals (b') and (d'') comes from the difference between the captured partial screen and the processed partial screen shown in FIG. From the rise of the signal (b') to the rise of the output command signal, this length is the same as the time allowed for the processing section 11 of the unit processor 3.

A signal (e') indicates the output of the delay circuit 91, and the output of the unit signal processor 3 is indicated as being on.

The delay circuit 91 is placed in a tri-state state by the output command signal (d') of the unit signal processor 4, and the output of the unit signal processor 4 is read out by the signal (d'). signal(
0 is obtained. Here, the portion marked A indicates the delayed output of the unit signal processor 3, and the portion marked B indicates the output of the unit signal processor 4.

Although the control signals for only unit processors 3 and 4 have been described in FIG. 3, unit processors 5 and 6 are also controlled in the same manner. Therefore, the output of each unit signal processor is successively read out to the output terminal 8 in FIG. 1, as shown in signal (g), with a delay of four sample times from the synchronization signal applied to the terminal 1. Here, C and D are the outputs of the unit signal processors 5 and 6, respectively.

Therefore, the result of processing one screen worth of video is obtained.

FIG. 4 shows unit signal processors 3, 4, 5, 6. This is an embodiment of the control unit 13 used in the synchronization signal input terminal 20. Clock signal input terminal 21. Capture signal output terminal 22, execution signal output terminal 23. Output command signal output terminal 2
49 column counter 252 row counter 26. Read-only memory 27.28. It consists of gate circuits 29, 30, and 31.

The read-only memory 27 outputs 3 bits, and the first bit is 1 if the value of the input address matches the line number of the captured screen.
The other bits are programmed to output zero, and the second bit outputs 1 if the input address value is the line number on the screen at the time you want to output the execution command, and zero for the others. The third bit is set to 1 if the input address value matches the line number on the processing screen.
Others are programmed to output zero.

Also, the read-only memory 28 similarly has a 3-bit output and the first
The bit is programmed to output 1 if the value of the input address matches the column number on the capture screen, and 0 otherwise. It is programmed to output 1 for the column number on the screen and 0 for the others, and the third bit outputs 1 for the column number of the input address that matches the column number on the processing screen. Programmed to output zero.

When the synchronization signal is input from the terminal 20, the column counter 25
and row counter 26 are reset and both output zero. Assuming that we are now considering the control section of the unit processor 3 that processes the first section in FIG. ff1j in the third bit
j, and the second bit is nOu. Also, due to the value 0 of the line counter, the read-only memory 27 sets ``1'' to the first bit indicating the capture screen and the third bit indicating the output screen.
, and the second bit is '0''. Therefore, 29, 30, and 31 are the input signal output terminals 22, respectively.
"1" is output to the execution signal output terminal 23, °0 is output to the execution signal output terminal 23, and "1" is output to the output command output terminal 24. Every time a sampled video signal is applied to the terminal 2 in FIG. 1, a signal is applied to the clock terminal 21 in FIG. 26 is advanced one step and the column counter 25 returns to zero. Therefore, the first bit of the read-only memory 28, 27 outputs '1' as long as the column and row counters 25 and 26 respectively indicate the column and row belonging to the captured screen, and the gate 29 therefore outputs '1'. ``'1'' terminal 2 for the specimen position belonging to the screen
Output to 2.

Similarly, only when the column counter 25 and row counter 26 indicate the values of the column and row that should instruct the start of processing, the read-only memory 2
8.2'7 outputs °°1'', and at this time the gate 30 outputs "1'" to the terminal 23 as an execution signal.

Similarly, when the column counter 25 and row counter 26 indicate the column and row corresponding to the output screen, the read-only memory 28.2
7 outputs IT, and as a result, the gate 31 outputs the terminal 24.
outputs '1''' as an output command signal. FIG. 5 shows an embodiment of the processing section in the unit signal processors 3, 4, 5.6 of FIG. .Input terminal 43 from the intake section.
Address output terminal 44 to the input section. Output terminal 45 to the output section. Address output terminal 46 to the output section, write signal output terminal 47 to the output section. Execution signal input terminal 48. It is composed of a capture unit output prohibition signal output terminal 49. The signal processor 40 is the NE described in the second document of the present invention.
It is assumed that a PD7720 manufactured by C is used.

, the PD file 720 is a signal processing processor that has internal multipliers and adders and has a unique bus configuration, but the details are given in the second document. , PD7720 can perform interrupt processing when a signal arrives at the interrupt input terminal (INT), and also has a programmable output bit PL.
, has P2. Input/output is performed via a bidirectional parallel bus (D); if a signal is coming to the write terminal (W), it is used as an input direction bus, and if no signal is coming to the write terminal (W), it is used as an output direction bus. Used as a bus.

Now, when an execution signal from the control unit 13 in FIG. 1 is applied to the terminal 48 in FIG. 5, the signal processor 40 starts digital signal processing as an interrupt process. For this reason, input data from the import unit 10 shown in FIG.
1 to ``1''. At this time, the gate 42 outputs 0'', data on the port D can be output from the signal processor 40 to the outside, and the address is stored in the register 41.

Next, when Pl is set to '0'', the contents of register 41 will be changed to terminal 4.
4 to the receiving unit 10, and the corresponding signal is inputted from the terminal 43 to the input terminal ``D''.

Similarly, in order to transfer the processed data from the signal processor 40 to the output unit 12, an address is specified to the output unit 12, so the necessary address is prepared in the boat D and the data is transferred from the bit output port P1 to the bit output port P1. and writes the address to the register 41. This address is output to the output terminal 46.
is transmitted to the output section 12 via. Next, prepare the processed data on boat D and use it from bit output port P2 to H11.
Outputs 9. At this time, the gate 42 outputs 0'', the port D becomes a state where the signal processor 40 outputs to the outside, and the data on the D port is notified to the input unit via the output terminal 49 that output is prohibited. is transmitted to the output section via terminal 45.Bit output capo) I of P2
tII9 is transmitted to the output section through terminal 47, and is transmitted to terminal 4.
It instructs to write the data transmitted from 5 to the output section.

The present invention can be implemented in the manner described above.

In the embodiment of the present invention, a read-only memory is used in the control unit, but by replacing it with a random access memory or the like, the predetermined positions of the captured partial image and the processed partial image can be dynamically changed. You can also do it.

Furthermore, in the present invention, the control section for specifying the position of the captured partial image and the processing partial image is distributed to each unit signal processor, but the configuration is such that these are centralized and only the control signal is distributed to each unit processor. can also be easily achieved. All these variations belong to the invention.

(Effects of the Present Invention) As seen above, according to the present invention, video signals are processed by a plurality of unit signal processors without communicating with each other, and without any digital signal processing at the boundary between the unit signal processors. Advanced digital signal processing can be achieved without any impact. Therefore, by using many unit signal processors, real-time digital signal processing can be applied to video signals.

In addition, the unit signal processors arranged in a pipeline differ only in the designation of the capture screen and processing screen, and the processing section of each unit signal processor should be processed by the same digital signal processing program, so the program development is also difficult. Programming can be done easily only for a single signal processor, and programs for other unit signal processors can be made by copying the developed program.

Furthermore, since only the acquisition screen and processing screen areas differ between unit signal processors, many unit signal processors are arranged in a pipeline, the output of a failed unit signal processor is prohibited, and other spare unit signal It can also be used as a highly reliable signal processing processor because it can recover from a failure by simply changing the definitions of the processor's capture screen and processing screen.

In addition, since the unit signal processors are separated by delay circuits, even if a large number of unit signal processors are installed, the early signals, input signals, and output video signals to be transmitted are transmitted at different timings. Mistakes can be avoided.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the principle of the invention, Fig. 3 is a diagram showing the operation timing of Fig. 1, and Fig. 4 is a part of Fig. 1. FIG. 5 is a diagram showing a part of FIG. 1. In the figure, 1... Synchronization signal input terminal 2... Video signal input terminal 3.4, 5, 6... Unit signal processor 7
... Synchronization output terminal 8 ... Video output terminal 10 ... Importing section 11 ... Processing section 1
2...Reading unit 13...Control unit 81
．． 82, 83, 91, 92.93... Delay circuit. \, -7 Fig. 2 Fig. 3 ((f) Output ridge 1 c force) (Tsurij?ili+3 δ ABCDABC Fig. 4

Claims (1)

[Claims] 1. A control unit that generates a predetermined input partial screen position signal and output partial screen position signal from a synchronization signal that indicates the start of one screen of a video signal such as a television signal, and an input partial screen position signal that is input from the control unit. a capture unit that captures a partial screen signal specified by the input partial screen position signal of a separately input video signal; a processing section that performs signal processing before the next screen capture starts; and a processing section that is connected to the output side of the processing section and stores the processing results of the processing section, and the output partial screen position that is separately input from the control section. a plurality of unit processors comprising an output unit that outputs the stored processing result at a partial screen position designated by the signal; and a plurality of unit processors that delay the synchronization signal and the video signal by one sample at each sample time. means for inputting the synchronization signal delayed through the delay circuit and the video signal to one unit processor for each delay circuit; means for sequentially combining the outputs of the plurality of connected unit processors with the outputs of the unit processors having a smaller delay amount due to the delay circuit to the unit processor outputs having one more delay amount due to the delay circuit; The predetermined output partial screen is processed so that there is no overlap among the unit processors, and the predetermined output partial screen is processed so as to allow overlap, and the input/output signals of each unit processor are connected in a pipeline. Features a real-time video processor.