JPS61123170A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device having the large allowance of operation, in which there is no operation instability due to interferences among signal lines for an array section, by making the thickness of signal lines for the array section thinner than that of wirings in sections except the array section. CONSTITUTION:A semiconductor memory storage consists of a data line 1A for a cell array section, a peripheral-circuit section metallic wiring 13, one electrode 9 for an information storage capacitance and a word line 2. The thickness of the data line 1A is formed in size smaller than the wiring 13 for a peripheral circuit. Accordingly, opposite areas between adjacent data lines 1A are reduced, and the changes of potential of the data lines are not prevented by a capacitive coupling between the data lines 1A, thus enabling circuit operation having the degree of allowance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor integrated circuit device, and particularly to an improvement of a semiconductor integrated circuit device equipped with an array section having a plurality of signal lines that are undesirable for mutual interference. .

A semiconductor memory device will be described below as an example.

[Conventional technology]

2. Description of the Related Art Conventionally, there is a readout circuit shown in FIG. 2 that has been commonly used in semiconductor memory devices.

In the figure, (la) and (lb) are data lines, (2a)
is a word line, (2b) is a dummy word line, (3) is a data line (la) K: one of the multiple memory cells that can be connected, (4) is its information storage capacity, (5) is a dummy A memory cell, (6) is an information storage capacity of a dummy memory cell (5), (7) is a sense circuit, and (8) is a signal line for driving the sense circuit.

The operation of this readout circuit will be explained based on the waveform diagram shown in FIG. In Fig. 3, ■2 is the waveform of the word line (2a) and the dummy word line (2b), v8
is the sense circuit, the waveform of the electric signal line (8), "lx, v
Ib indicates the waveform of the data line (1aL (lb)).

First, word line (2a) Th and dummy word line (2b
) rises from a low level to a high level, the information storage capacity t
A slight potential change occurs in the data lines (la) and (11)) due to the amount of charge accumulated in (4) and (6).

Next, the sense circuit driving signal line (8) becomes cylinder level, the sense circuit (7) operates, and the data line (la)? (11
)) K A large potential difference appears.

For example, there is a method of configuring the above readout circuit on a semiconductor substrate as shown in FIG. 4. The cross-sectional structure taken along the v-Y plane in FIG.
) is a data line, (2) is a word line, and (9) is one electrode of the information storage capacitor.

An example of a method of configuring a semiconductor memory device equipped with a readout circuit as described above is shown in FIG. 6. In FIG. The peripheral circuit section (2) for controlling operations is a group of wiring lines for exchanging data and signals between the cell array section a1 and the peripheral circuit section (b).

A conventional cross-sectional structure of the above semiconductor memory device is shown in FIG. In the figure, (1) is the data line of the cell array section, (6) is the metal wiring of the peripheral circuit section, and (9) is the data line of the cell array section.
is one electrode of the information storage capacitor, and (2) is a word line. The data line (1) and the metal wiring (to) of the peripheral circuit are formed in the same process.

[Problems that the invention is supposed to solve]

Since conventional semiconductor memory devices are configured as described above, a capacitance may occur between the data lines (la) and (lb), and the existence of this capacitance reduces the operating margin of the readout circuit. There was a problem. Such a problem also occurs when a semiconductor integrated circuit device includes an array section having a plurality of signal lines in which interference with each other is undesirable.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device which has a large operational margin and is free from operational instability due to interference between signal lines in an array section.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, the thickness of the wiring in the play part having two or more wirings arranged parallel to each other and the peripheral circuit other than the array part is changed to reduce the thickness of the wiring in the array part. It is something.

[Effect]

Reducing the wiring thickness in the present invention reduces the parasitic capacitance formed between adjacent wirings and reduces interference between wirings.

〔Example〕

FIG. 1 is a cross-sectional view showing the structure of an embodiment of the present invention. The same reference numerals as in the conventional example shown in FIG. 7 indicate the same parts, and the explanation thereof will be omitted. In FIG. 1, (IA) is the data line of the cell array, which is the main point of this embodiment, and is made of the same metal as the metal wiring α of the peripheral circuit, but is formed with a smaller thickness than that.

By reducing the wiring thickness of the data line (IA), as can be seen from FIG. 5, the opposing area between adjacent data lines can be reduced, and when the readout circuit is in operation, Capacitive coupling between the data lines does not impede changes in the potential of the data lines, making it possible to operate the circuit with sufficient operating margin.

Furthermore, since the thickness of the wiring is not reduced in the peripheral circuit section, the circuit operation in the peripheral circuit section is not affected.

In the above embodiment, a case has been described in which the metal wiring in the cell array section is formed by a data line, but the word line may be formed of a metal wiring, and the same effects as in the above embodiment can be obtained.

Further, the present invention is not limited to memory arrays, but can be widely applied to semiconductor integrated circuit devices having an array section having a plurality of signal lines where the presence of interference is undesirable.

〔Effect of the invention〕

As described above, according to the present invention, the thickness of the metal wiring in the array portion and the metal wiring in the peripheral circuit portion are changed, and the thickness of the metal wiring in the array portion is reduced. This has the effect of increasing the operating margin within the array without affecting the circuit operation in the array.

[Brief explanation of the drawing]

Figure 1 is a cross section showing the configuration of a semiconductor memory device that is an embodiment of the present invention, Figure 2 is a circuit diagram showing a readout circuit commonly used in semiconductor memory devices, and Figure 3 is an f4
FIG. 2 is a waveform diagram showing the circuit operation; FIG. 4 is a plan view showing an example of the structure of the memory cell section of the seven readout circuits conventionally used in semiconductor memory devices; 6 is a block diagram showing the structure of a general semiconductor memory device, and FIG. 7 is a sectional view showing the structure of a conventional semiconductor memory device. In the figure, (IA) is the signal line (data line) of the array section.
, (1G is the play part, (6) is the part other than the play part (
(peripheral circuit section), 03 is wiring for parts other than the array section 0 The same reference numerals in each figure indicate the same or equivalent parts 0

Claims (5)

[Claims] (1) In an array unit having a plurality of signal lines in which mutual interference is undesirable, the thickness of the signal lines in the array unit is made smaller than the thickness of the wiring in parts other than the array unit. Features of semiconductor integrated circuit devices. (2) The semiconductor integrated circuit device according to claim 1, wherein both the signal line and the wiring are made of a metal conductor layer. (3) A semiconductor integrated circuit device according to claim 1 or 2, wherein the array section is a memory cell array section. (4) The semiconductor integrated circuit device according to claim 3, wherein the signal line is a data line for reading information from a memory cell or writing information to the memory cell. (5) The semiconductor integrated circuit according to claim 3, wherein the signal line is a word line for selecting a memory cell for reading or writing information, and a dummy word line for driving a dummy memory cell. Device.