JPS61122593U - - Google Patents
Info
- Publication number
- JPS61122593U JPS61122593U JP400485U JP400485U JPS61122593U JP S61122593 U JPS61122593 U JP S61122593U JP 400485 U JP400485 U JP 400485U JP 400485 U JP400485 U JP 400485U JP S61122593 U JPS61122593 U JP S61122593U
- Authority
- JP
- Japan
- Prior art keywords
- alarm
- signal
- selection
- input
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000004397 blinking Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 1
Description
第１図はこの考案に係る時計装置の一実施例を
示すブロツク回路構成図、第２図は同実施例の動
作を説明するためのフローチヤート、第３図は従
来の時計装置の構成を示すブロツク回路図である
。
１１…表示部、１１ａ…現在時刻表示部、１１
ｂ…アラーム選択表示部、１１ｃ…アラーム時刻
表示部、１２…キーボード、１２ａ…アラームモ
ード設定キー、１２ｂ，１２ｃ…アラーム選択キ
ー、１２ｄ…時刻入力キー、Ａ…現在時刻設定回
路、Ｂ…第１のアラーム時刻設定回路、Ｃ…第２
のアラーム時刻設定回路、３５，３６…一致回路
、３７…アラーム音発生回路、４０…タイマ回路
、４１，４２…誤り検出回路、４３，４４…フラ
ツシング回路。
Fig. 1 is a block circuit configuration diagram showing an embodiment of a timepiece device according to this invention, Fig. 2 is a flowchart for explaining the operation of the same embodiment, and Fig. 3 shows the configuration of a conventional timepiece device. FIG. 3 is a block circuit diagram. 11...Display section, 11a...Current time display section, 11
b...Alarm selection display section, 11c...Alarm time display section, 12...Keyboard, 12a...Alarm mode setting key, 12b, 12c...Alarm selection key, 12d...Time input key, A...Current time setting circuit, B...First alarm time setting circuit, C...second
alarm time setting circuit, 35, 36... matching circuit, 37... alarm sound generating circuit, 40... timer circuit, 41, 42... error detection circuit, 43, 44... flushing circuit.
Claims (1)
刻設定信号を生成して該現在時刻設定信号に応じ
て現在時刻を表示し、アラームモード設定キーの
設定状態で複数のアラーム時刻を選択するアラー
ム選択キーの選択状態を検出してアラーム選択信
号を生成し、このアラーム選択信号に応じて複数
のアラーム時刻設定回路の一つを動作させ時刻入
力キーの操作により入力される時刻を記憶させて
アラーム時刻設定信号を生成し、前記アラーム選
択信号を入力してアラーム選択状態を表示すると
共に該アラーム選択信号によつて選択されたアラ
ーム時刻設定信号を入力してそのアラーム時刻を
表示し、前記現在時刻設定信号を前記各アラーム
時刻設定信号とそれぞれ比較し各信号が一致した
ときアラーム音を発生するタイマ装置において、
前記複数のアラーム時刻設定回路毎に設けられそ
れぞれ前記時刻入力キーの操作によるアラーム時
刻入力の誤りを検出して操作ミス検出信号を発生
する操作ミス検出回路と、前記操作ミス検出信号
の発生に応じて前記アラーム選択表示を点滅させ
ることによりどのアラーム時刻の入力がミスした
かを響報する第１の操作ミス警報手段と、前記操
作ミス検出信号の発生に応じて前記アラーム音発
生回路を動作させることによりアラーム時刻の入
力ミスがあつたことを警報する第２の操作ミス警
報手段とを具備したことを特徴とする時計装置。 Selection of an alarm selection key that generates a current time setting signal by counting the reference clock signal, displays the current time according to the current time setting signal, and selects multiple alarm times in the setting state of the alarm mode setting key. Detects the state and generates an alarm selection signal, operates one of the plurality of alarm time setting circuits in response to the alarm selection signal, stores the time input by operating the time input key, and generates the alarm time setting signal. generate the alarm, input the alarm selection signal to display the alarm selection state, input an alarm time setting signal selected by the alarm selection signal to display the alarm time, and input the current time setting signal to the alarm selection state. In a timer device that compares each alarm time setting signal and generates an alarm sound when each signal matches,
an operation error detection circuit that is provided for each of the plurality of alarm time setting circuits and that detects an error in alarm time input due to operation of the time input key and generates an operation error detection signal; a first operation error alarm means for sounding which alarm time input has been erroneously made by blinking the alarm selection display; and operating the alarm sound generation circuit in response to generation of the operation error detection signal. 1. A clock device comprising: a second operation error alarm means for warning that an error has been made in inputting an alarm time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP400485U JPS61122593U (en) | 1985-01-16 | 1985-01-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP400485U JPS61122593U (en) | 1985-01-16 | 1985-01-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61122593U true JPS61122593U (en) | 1986-08-01 |
Family
ID=30479159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP400485U Pending JPS61122593U (en) | 1985-01-16 | 1985-01-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61122593U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59131191A (en) * | 1976-02-09 | 1984-07-27 | Yokogawa Hewlett Packard Ltd | Electronic timepiece |
-
1985
- 1985-01-16 JP JP400485U patent/JPS61122593U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59131191A (en) * | 1976-02-09 | 1984-07-27 | Yokogawa Hewlett Packard Ltd | Electronic timepiece |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61122593U (en) | ||
| JPS6038237Y2 (en) | Electronic clock with alarm | |
| JPS6358791U (en) | ||
| JPH0649027Y2 (en) | Timer device for radio controlled transmitter | |
| JPH0187292U (en) | ||
| JPS6331394U (en) | ||
| JPS6227909Y2 (en) | ||
| JPS63195424U (en) | ||
| JPS61119791U (en) | ||
| JPS6358792U (en) | ||
| JPS6223151Y2 (en) | ||
| JPS6225747Y2 (en) | ||
| JPS6156592U (en) | ||
| JPS61122594U (en) | ||
| JPH01134295U (en) | ||
| JPH0241196U (en) | ||
| JPS6388782U (en) | ||
| JPS6291285U (en) | ||
| JPS6230185U (en) | ||
| JPH0235092U (en) | ||
| JPS6331393U (en) | ||
| JPS6331392U (en) | ||
| JPS62118274U (en) | ||
| JPS61131690U (en) | ||
| JPS6215829B2 (en) |